The SoC from Cortina Systems known by the project name Gemini was concieved by Storlink Semiconductor in the early 2000s, apparently with heavy consultation from Faraday Technology. The company changed their name into Storm Semiconductor, and then Cortina acquired Storm Semiconductor in 2008. It seems to have been evolved from an even earlier SoC named SL2312. Lepus seems to be a code name for Gemini.
The SoC is a family of the following chips:
- SL3512/CS3512 code name Bulverde and 18x18 pins out.
- SL3516/CS3516 code name Lepus (I think) - this has one additional on-chip peripheral compared to SL3512/CS3512: CIR (consumer infrared), and has 20x20 pins out.
- SL3518/CS3518 a dual-core CPU in the same family. I don't know if SL3518/CS3518 was ever produced.
This SoC has an ARMv4 ISA and is based on the Faraday FA526 third-party ARM IP core. It can sometimes be hard to find the right tools and no major distributions support the ARMv4 ISA. The typical userspace is built using OpenWrt or OpenEmebedded. I try to support as many as I can with OpenWrt, where I am contributing the Gemini port.
I am trying to collect vendor tree code at GitHub. Please contribute if you have newer GPL sources than what I have. The code seems to have been partly written by MontaVista under consultant contract to Storlink.
The procedure is likely similar on all the Gemini platforms. I was initially using the ITian SquareOne Smart Storage Server, and brought that and other devices up to full mainline Linux support. I got this unit from Florian at OpenWRT to have a Gemini (ARM FA526 based) SoC hacking target.
It is pretty easy for an experienced hacker to get any of these devices running with the latest kernel and full hardware support. Most of the heavy lifting is already done and landed upstream. If you have one of these and you don't know what to do with it or very much want support for it, send it to me (no strings attached) and I will try to fix it up. I will likely try to solder in a UART so it is risky. (linus.walleij@linaro.org)
Systems using the Gemini/SL3512:
- Storm Semiconductor SL93512R_BRD reference design (supported upstream, devicetree)
- D-Link DNS-313 (NAS) (supported upstream, devicetree)
- MRT Communication 35HD-DUAL-NAS-E (SL3512c2, hacking page)
- Raidsonic IB-NAS4210B "ICY BOX"
- Teltonika RUT1xxx (RUT104, RUT105, supported upstream, devicetree)
- Wiliboard WBD-111 (supported upstream, devicetree, OpenWRT page, product datasheet)
- Wiliboard WBD-222 (supported upstream, devicetree, hardware manual)
Systems using the Gemini/SL3516:
- Storm Semiconductor SL93516N Gigabit Storage Router Gateway reference design (datasheet)
- Storm Semiconductor SL93516R Gigabit Storage Router Gateway reference design (datasheet)
- Argosy HD354N (forum post)
- D-Link DIR-685 - router with fancy LCD display and all (supported upstream, devicetree)
- Digitus DN-7024 (german hacking page)
- Edimax NS-2501
- Edimax NS-2502 (NAS forum thread, supported upstream, devicetree)
- I-O Data LANDISK HDL-GSxxxx (PCB photo)
- ITian SquareOne SQ201-W - router and NAS (supported upstream, devicetree)
- MRT Communication 35HD-QUAD-NAS-E - this one is using the LCD hardware and possibly also the RAID accelerator (hacking page)
- Planex MZK-NAS01SG (according to PCB picture, vendor page)
- Planex MZK-NAS02SG (vendor page)
- Raidsonic IB-NAS4220B "ICY BOX" (supported upstream, devicetree, zImage)
- SSI 1328 (supported upstream, devicetree)
- Thecus N199 (manufacturer page)
- Thecus N299 (board photo)
- Vantec NexStar-FX GigaNAS NST-610NU N1 (WikiDev page)
Unknown SoC (SL3512 or SL3516, suspect SL3512 on all NAS products):
- Atlantis A06-NASG302D (vendor page)
- Claxan CL-NAS-1000
- Datastor/Omnitech Innovation NAS3000
- Dotop Technology MLM-3521
- FantomDrives (MicroNet) G-Force MegaDisk 1000, 1500 and 2000
- Fitivision Technology NVR-1000
- Freecom Network Drive Pro
- Intellinet Gigabit SATA NAS Model 503662
- MCS NAS1000 and NAS2000
- Mvix MvixBOX WDN2000
- Planet NAS-7101
- Planet NAS-7102
- Sans Digital MN2L
- Sarotech Wizplat NAS-20
- Stardom Storage Solutions SL3620-2S-LB2
- Verbatim Gigabit NAS (old product page)
Out of scope
- MRT Communication DualBay GIGANAS (uses SL3316)
It turns out that many of the components inside the Gemini machines are actually off-the-shelf IP blocks from Faraday Technology, an SoC design firm in Taiwan, that has been around since the 1990ies.
Getting into Gemini Systems
All Geminis are pretty similar with regards to serial ports etc. See my pages for the D-Link DNS-313, D-Link DIR-685 and ITian SquareOne for examples of how I attached UART and accessed the Internals.
Most systems are 19200 bps by default but some are occasionally at 115200 bps.
Getting OpenWRT up on it
As per 2018-02-20 I managed to rebuild and boot OpenWRT on the DIR-685 and DNS-313. Since then, all patches I developed have been merged into the upstream OpenWrt repository. The steps taken to build OpenWrt are:
- Clone the latest OpenWRT git tree
- cd openwrt
- make menuconfig
- Target system Cortina System CS351x
- Target profile [YOUR DESIRED ROUTER]
- Exit and save config
- make
- (build build build build)
- A usable image appears in bin/targets/gemini/raidsonic/openwrt-gemini-[YOUR_DESIRED_ROUTER]-factory.bin (or similar)
Compiling the kernel
This mostly details how to get an upstream bleeding-edge kernel compiled and booting on the Gemini devices.
The toolchain from OpenWRT should work just fine to build userspace, I just haven't tried it. For kernel compiles I just use the latest Linaro ARM toolchain.
You can use my makefile and initramfs to get to a prompt. Copy the rootfs-gemini.cpio to your $HOME directory, then put the gemini.mak file in your Linux base directory and type:
make -f gemini.mak config && make -f gemini.mak build
The initramfs config option to boot from a RAM resident busybox will take precedece, so if you want to use OpenWRT as rootfs you need to disable that in the kernel build.
- The binary ARM-provided ARM GCC toolchain is what I use for compilation
- My gemini.mak Makefile
- My rootfs-gemini.cpio rootfs with Busybox (generated by this script) this can be useful for testing.
Gemini SoC Kernel TODO
Convert the platform to MULTI_IRQ (patch, merged for v4.12)Support the Faraday FTINTC010 interrupt controller:Add DT bindings for the Gemini interrupt controller (patch, merged in v4.11-rc1)Add a new Gemini irqchip implementation (patch, merged in v4.11-rc1)Rewrite the DT bindings to reflect that it is a Faraday part (patch, merged for v4.12)Refactor the irqchip to reflect that it is a Faraday part (patch, merged for v4.12)Implement low/high level IRQs properly (patch, merged for v4.12)Make a patch making Moxart use this driver too (patch, merged for v4.12)Check if Aspeed is using this - it's notCheck Andestech arch/ndes32, Moschip mcs8142 (OpenWRT), str8132, Grain Media GM8126/GM8136S/GM8135S/GM8181
Support the Faraday FTTMR010 timer/clocksource:Add DT bindings for the Gemini clocksource (patch, merged in v4.11-rc1)Add a new Gemini clocksource driver (patch, merged in v4.11-rc1)Rewrite the DT bindings to reflect that it is a Faraday part (patch)Refactor the clocksource driver to reflect that it is a Faraday part (patch)Refactor the clocksource driver to handle a generic part with just a clk reference (patch)Augment timer driver to get clock and rate from the clock driver (patch merged for v4.13)Remove the Gemini-specific code when there is a proper clock driver for Gemini (patch merged for v4.13)Switch Moxart to use this driver (patch merged for v4.13)Switch Aspeed to use this driver (patch merged for v4.13)Optimize down-counting sched_clock() (patch merged for v4.13)Add support for delay timers (patch merged for v4.13)- Augment timer driver to support 32kHz
Support the Faraday GPIO controller:Add DT bindings for the GPIO controller (patch, merged in v4.11-rc1)Add a new GPIO driver (patch, merged in v4.11)Augment the DT bindings to reflect that it is a Faraday part (patch, merged for v4.12)Refactor the GPIO driver to reflect that it is a Faraday part (patch, merged for v4.12)Propose a patch to switch Moxart over to this driver (patch, merged for v4.12)Grab the silicon clock (patch applied for v4.20)Add debounce support (patch applied for v4.20)Convert to immutable irqchip
Add a Gemini combined clock and reset controller driver:Add device tree bindings for the Gemini clocks (patch merged for v4.13)Add device tree bindings for the Gemini reset controller (patch merged for v4.13)Add a clock driver for the Gemini clocks (patch merged for v4.13)Add a reset driver for the Gemini reset controller (patch merged for v4.13)Merge the reset driver into the clock driver due to DT layout (patch mergefd for v4.13)Augment the Gemini SoC DTSI to assign clocks to all IP blocks that have it (patch merged for v4.13)Augment PCI driver to grab a clock (patch merged for v4.13)Fix PCI driver to fetch clocks unconditionally so probe deferral works (patch merged for v4.13)Augment timer driver to get clock and rate from the clock driver (patch merged for v4.13)Rewrite the reset controller to be part of the clock controller due to DT layout (patch merged for v4.13)Augment the Gemini SoC DTSI to assign reset lines to all IP blocks that have it (patch merged for v4.13)Use the reset controller in the SATA driver, where it is required (merged as part of the IDE/SATA driver for v4.13)Augment USB driver to grab a clock (patch merged for v5.0-rc1)- Augment timer driver to support 32kHz
Add a Gemini pin controller:Add device tree bindings for the Gemini pin controller (patch merged for v4.14)Add a Gemini pin controller driver (patch, merged for v4.14)Augment all Gemini device trees, supplying proper pin states and tying the handles to the right devices (patch)Retire old flash pin muxing handling (patch)Retire old IDE muxing handling (patch)Introduce explicit IDE pin muxing state (patch)Retire old PCI clock output enable handling (patchSelect the pin controller in the Gemini Kconfig (patch merged for v4.14)Add skew/delay pin config support for the ethernet (patch merged for v4.15)Add drive strength pin group config support for the ethernet, PCI and IDE (patch merged for v4.16)- Clean up fixed links after ourselves properly (requested by Andrew Lunn)
Support the Faraday FTRTC010:Add DT bindings and probing to the Gemini RTC driver (patch, merged in v4.11-rc1)Handle block clocks (patch merged for v4.13)Augment the DT bindings to reflect that it is a Faraday part (patch merged for v4.13)Refactor the RTC driver to reflect that it is a Faraday part (patch merged for v4.13)Investigate the Moxart RTC, it is clearly not the same hardware, but is it another Faraday block? - NO- Support 32kHz mode properly
Support the MTD physmap extensions:Convert the platform and all existing boards plus mine to device tree (patches merged for v4.12)Add top-level DT bindings for the Gemini (patch, merged for v4.12)Core device tree support for the Gemini (patch, merged for v4.12)Add a DTSI for the Gemini SoC and a DTS for SQ201 (patch, merged for v4.12)Add a DTS for the Raidsonic NAS IB-4220-B (patch, merged for v4.12)Add a DTS for the Teltonika RUT1xxx (patch, merged for v4.12)Add a DTS for the Wiliboard WBD-111 (patch, merged for v4.12)Add a DTS for the Wiliboard WBD-222 (patch, merged for v4.12)
Delete all the boardfiles (patch, merged for v4.12)Convert to SPARSE_IRQ (patch, merged for v4.12)Convert to PATCH_PHYS_TO_VIRT and AUTO_ZRELADDR (patch, merged for v4.12)Convert to multiplatform (patch, merged for v4.12)Add a Gemini defconfig (patch, merged for v4.12)Upstream the Faraday FTWDT010 watchdog driverAdd DT bindings for the Gemini watchdog (patch, merged in v4.11-rc1)Add a new Gemini watchdog driver (patch, merged in v4.11-rc1)Add the watchdog to the SoC DTSI file (patch, merged for v4.12)Augment the DT bindings to reflect that it is a Faraday part (patch merged for v4.16)Refactor the watchdog driver to reflect that it is a Faraday part (patch merged for v4.16)Augment FTTWD010 driver to make interrupts optional (patch merged for v4.16)Add PCLK and compatible to Gemini and MOXA ART (patch merged for v4.16)- Augment FTTWD010 driver to support PCLK and EXTCLK properly (patch)
- Augment FTTWD010 driver to support watchdog restart (patch)
- Augment the DT bindings to handle MOXA ART and Aspeed (patch)
- Augment FTTWD010 driver to support Moxart (patch)
- Augment FTTWD010 driver to support Aspeed (patch)
- Add PCLK and compatible to Aspeed (patch)
- Retire old MOXA ART and Aspeed drivers (patch)
Upstream the Faraday FTPCI100 host bridge driver (this is also used by the Andestech SoC)Add DT bindings for PCI Host Bridge (patch v4, merged for v4.12)Add a driver for the Faraday PCI Host Bridge (patch v4, merged for v4.12)Select MIGHT_HAVE_PCI on the Gemini (patch dropped - not needed, multiplatform already selects this)Add the PCI Host Bridge to the SoC DTSI file (patch v3)Enable the FTPCI100 driver on the boards that use it
Upstream the Gemini power controller driverUpstream a Lepus SATA driver (vendor driver in drivers/ide/arm/sl2312ide.c and drivers/scsi/sata0_storlink.c)Figure out if this is also a Faraday part, FTIDE010 - guessing it isFix a bug in the libata devres core (patch - DROPPED was not even a bug, my bad)Add DT bindings for FTIDE010 (patch merged for v4.13)Add DT bindings for the Gemini SATA bridge (patch merged for v4.13)Add a driver for FTIDE010 and Gemini SATA bridge (patch merged for v4.13)Add FTIDE010 blocks to the Gemini SoC DTSI file and enable the first FTIDE010 block on the SQ201 and NAS4220b (patch merged for v4.13)Select the IDE/SATA/FTIDE010 driver from the Gemini defconfig (patch)
Upstream the Faraday FTDMAC020 DMA controllerClean up the ARM PL08x driver (patches merged for v4.12)Augment the ARM PL08x DT bindings to cover FTDMAC020 (patch merged for v4.13)Augment the ARM PL08x DMA driver to handle the FTDMAC020 (patch merged for v4.13)Add the FTDMAC020 to the Gemini DTSI file (patch merged for v4.13)Enable AMBA in the Gemini Kconfig so the FTDMAC020 can be selected (patch, merged for v4.14)Select the DMAC in the Gemini defconfig (patch)
Upstream a Faraday TVE200 (TV Encoder) driverAdd device tree bindings for the TVE200 (patch merged for v4.15)Add a DRM driver for the TVE200 (patch merged for v4.15)Refactor the TVE200 connector to use the panel bridge (patch merged for v4.15)Clean up the panel bridge support using KMS helper (patch merged for v4.15)Add the TVE200/TVC block to the Gemini SoC DTSI file (patch merged for v4.15)Add the proper panel entries to DTS files (i.e. D-Link DIR-685, patch merged for v4.16)Select the TVE200 driver in the Gemini defconfig (patch merged for v4.17)
Upstream a GMAC ethernet driver (vendor driver in drivers/net/sl351x*)Augment the Gemini pin control driver to handle GMAC0 and GMAC1 pin groups separately (patch merged for v4.15)Augment the Gemini pin control driver to support skew/delay settings (patch merged for v4.15)Augment the Gemini pin control driver to support drive strength settings on GMAC0 and GMAC1 (patch merged for v4.16)Create a SoC driver to handle BUS2 arbitration: this set-up was done in the ethernet driver in the vendor tree for some mystical reason (patch merged for v4.16)Create a device tree binding for the Gemini ethernet (patch merged for v4.16)Update and rewrite the old patch set from Miroslaw to v4.15-rc1 (patch merged for v4.16)Add the ethernet block to the Gemini SoC DTSI file (patch merged for v4.16)Augment the Gemini device trees to enable the ethernet driver (patch merged for v4.16)Enable the driver by default in the Gemini defconfig (patch merged for v4.17)Handle using both eth0 and eth1 on the same system (patch merged for v4.19)Handle jumboframes (patch merged for v4.19)Handle fixed links (to switch chips) on the ethernet properly (patch merged for v4.19)
- Activate the Faraday FOTG210 EHCI USB driver (Hans Ulli Kroll is looking at this)
The driver already exists in drivers/usb/host/fotg210-hcd.cAdd DT bindings for FOTG210 (patch merged for v5.0-rc1)Add DT probing for FOTG210 (patch)Handle PCLK in the FOTG210 driver (patch merged for v5.0-rc1)Add the FOTG210 to the Gemini SoC DTSI file (patch merged for v5.0-rc1)Activate driver by default in the Gemini defconfigFix to restart the HCD after port reset (patch merged for v5.3)- VBUS handling and OTG device mode handling using GPIO, a device-mode driver exists
Upstream a crypto driver (called "sl2312_ipsec" in the vendor tree, crypto/sl2312_ipsec_sw.c) - task completed by Corentin Labbe- Upstream a CIR infrared controller if a target using it can be found (vendor driver in drivers/char/gemini_cir.c)
- Upstream an LCD driver if a target using it can be found.
- Upstream a I2S/SSP sound driver if a target using it can be found (vendor driver in drivers/char/gemini_i2s.c and drivers/telephony/gemini_ssp.c, apparently mixed in with its telephony usecase).
- Kick the SL3518 second CPU into action if a target using it can be found.
Add a device tree for the Storm Semiconductor SL93516R Gigabit Storage Router Gateway reference design (patch)
OpenWRT TODO
- Kernel v6.1:
Switch to kernel v6.1- Activate the two new boards: SSI 1328 and Edimax NS-2502 as OpenWrt targets
Kernel v5.15Kernel v5.10Kernel v5.4:Bump the kernel patches to v5.4 (patch exist)Create a kernel config to v5.4 (patch exist)Switch to kernel v5.4 (patch exist)
Kernel v4.19:Bump the kernel patches to v4.19 (patch exist)Create a kernel config to v4.19 (patch exist)Switch to kernel v4.19 (patch exist)Add support for SL93512r (patch exist)
Links
- OpenGemini
- Last posting of the Faraday A320 SoC support using many of the same IP blocks
- OpenWRT git repo with latest patches
- Latest posting of the GMA ethernet driver
- Power controller driver - appeared out of nowhere
- Storm Semiconductor in the WayBack Machine (2008)
- Cortina Systems SL3516 page in the WayBack Machine
- Building SnapGear - there is a full v2.6.15 SL3516 patched kernel!
- Storlink based products at NAS-central lists a bunch of NAS devices using this SoC
- Gemini directory of NetBSD can give hints about how things work
- Some git tree with "non-OS" drivers for a bunch of Faraday IP blocks
- OpenWRT for StorLink SourceForge page - I think most of this has been merged into the OpenWRT codebase