920909/olga 1143.text # Change in chapter 5. - Bus timeout value changed # Change in chapter 5.3.3 - Bus timeout value changed # Change in chapter 6.1.3 - VME bus timeout value changed to 19us # Change in chapter 6.1.9.2 - EDC configuration bits in byte 0 (not 3). # Change in chapter 6.1.6.2 - Ethernet chip reset signal in status register # Change in chapter 6.2.5 - Ethernet chip reset signal in status register # Change in chapter 6.1.1 - Function code for pipeline operations. # Change in chapter 6.2 - Function code for pipeline operations. # Change in many chapters - Function code for pipeline operations. # Change in chapter 6.1.12.2 - Level of thinwire control is changed (not on first prototype though) # Change in chapter 6.1.12.2 - Page 0 access detection # Change in chapter 5.3.1 - Page 0 access detection # Change in chapter 5.2.8 - RESET instruction warning # Change in chapter 5.3 - Only SIMM module memory board are used # Change in chapter 5.3.3 - Global bus timeout value changed. # Change in chapter 6.1.9.3 - EDC memory control, removed # Change in chapter 6.1.9.1 - EDC memory control, totally rewritten # Change in chapter 6.1.9.2 - EDC memory control, totally rewritten Short hardware description of DS90-47 SBC ========================================= P R E L I M I N A R Y 1. Scope. This document briefly describes the hardware concept of the DS90-47 computer. Basic information about the hardware solutions will be given in order to properly develop all necessary hardware test routines, I/O drivers and interrupt handlers. 2. Objectives. The DS90-47 is a high performance, low cost, MC68040 based supermicrocomputer system primarily intended to support office automation, data communication, industrial control and advanced server applications. In the basic configuration it provides the following resources: - Two MC68040 microprocessors - Main memory error detection and correction logic - 2 opto isolated serial communication channels (ComC modules) - 3 high speed SCSI interfaces - Floppy interface - Extended expansion capabilities 3. Highlights. The hardware concept is optimized for highest price/performance ratio. A 128kb cache allows "sub-zero" waitstate performance at 33 MHz CPU clock frequency with expected hit rate greater then 90%. Up to 6 processors (each containing CPU and cache), can execute system and user tasks concurrently for highest performance. The main memory can be expanded to 1Gb (using 16Mbit memory chips). Up to 12 opto isolated serial channels can be added using low cost hardware (5262-00 boards). The hardware provides full-spec VME extension, making it possible for various VME bus masters to access main system RAM, as well as to access VME bus resources by the system CPU(s). Beside VME extension, the hardware provides support for proprietary 4680 I/O subsystem. Three high speed SCSI interfaces supported by a dedicated DMA processor, provides very fast data transfer between mass storage devices and main memory. Each interface provides single ended, asynchronous/synchronous capabilities with multimaster facility which can be useful for sharing mass storage devices among a number of computers, as well as for direct computer-to-computer communication. Data transfer rate will be up to 5 Mb/sec for each SCSI channel. Floppy interface supports all existing recording standards, like FM and MFM, various data transfer rates (250,500 or 1000 kb/sec), different sector length and various motor speed (300 or 360 rpm). Up to 2 floppy drives can be accessed alternately (4 drives with restictions on the last two ones). The dedicated MC68020 DMA processor is located on a private DMA bus together with a boot prom, ram memory and totally 4 fifo's. The fifo's are used to transfer the data between the SCSI channels and floppy controller to and from the main memory. The DMA processor is also used to boot up the system by loading the main memory with the appropriate code before removing the reset condition on the main processors. 4. CPU operations. 4.1 Logical address space. The maximum logical address space for any program runned on DS90-47 is 4 Gb. 4.2 Access types. The following access types are generated by the MC68040. Interactions with the external cache and memory is given as comments. Type Size Dir. Comment -------------------------------------------------------------------- Cache Push 16 Write Update cache if hit, line write to memory if INVALID or SHARED. Normal 1/2/4 Write Update cache if hit, write to memory if INVALID or SHARED. 1/2/4 Read From cache if hit else from memory. 16 Read From cache if hit else load cache using line read. Tablewalk 4 R/W Locked cycles when update. Move16 16 R/W Read part: From cache if hit else from memory using line read. Write part: Update cache if hit, line write to memory if INVALID or SHARED. Alternate 1/2/4 R/W Not used. Acknowledge 1 Read See 4.3. Note: Locked cycles are either normal or tablewalk accesses. Read part is always read from memory. Write part is always written to memory, cache will be updated on hit. 4.3 Interrupt system structure. Of the 7 possible interrupt levels in the system, 1 and 4-7 uses autovector. Vector 2 and 3 is delivered by the hardware at interrupt acknowledge time. Further identification of an interrupt source is possible by reading interrupt vector register associated with resp. interrupt level. The hardware provides the following interrupt sources: Processor 0: Level Source Vector source ------- ----------------------- ------------------------- 7 Push-button (NMI) Auto 6 Real-time clock 64 Hz Auto 5 Inter-plane attention Auto 4 VME interrupt level 4 Auto + VME interrupter 3 - 2 I/O subsystem CIO 1 VME interrupt level 1 Auto + VME interrupter Processor 1: Level Source Vector source ------- ----------------------- ------------------------- 7 Push-button (NMI) Auto 6 - 5 Inter-plane attention Auto 4 - 3 Serial comm. channels resp. SCC 2 - 1 - Processors 2-5: Level Source Vector source ------- ----------------------- ------------------------- 7 Push-button (NMI) Auto 6 - 5 Inter-plane attention Auto 4 - 3 - 2 - 1 - All CPU's recognize level 7 and 5 interrupts. CPU 0 and 1 will in addition to level 7 and 5 also recognize levels according to the tables. 5. Physical address space. The hardware solution provides two bus systems, the main bus and the DMA bus. The main bus has 4Gb physical address space. All system resources respond for various addresses in the address map and provide either acknowledge, retry or error response. A global but timeout function will give a bus error termination after 37-50us. The following table shows how system resources are mapped within the address space. 5.1 Address map. 5.1.1 Resources, physically attached to the main bus. Base address Width Size Type Item --------------- ------- ------- ------- -------------------------------- 00000000 L 2Gb RW Main memory 80000000 - 1Gb - DMA bus C0000000 L 256M RW VME extended space D0000000 L 16M RW VME standard space (16 times) E0000000 L 64k RW VME short I/O space E0200000 B 1 RW VME extended address register E0400000 B 1 RW VME interrupt mask register E0500000 B 1 RO VME interrupt readout E0FFFFFv W 2 RO VME intack F0000s03 B 1 RW SCSI chip address register F0000s13 B 1 RW SCSI chip data register F0C00003+(n^8) B 1 RW CPU attention (n = 0-5) F0C00703 B 1 RW CPU reset control F0C00010 - 1 WO LAN controller port F0C00010 - 1 RO LAN controller channel attention F0C00020 L 1 RO Watchdog kick F0C00020 L 1 WO Timer interrupt reset F0C00030 L 1 RO EDC - Error data register F0C00030 B 1 WO EDC - Configuration register F0C00038 L 1 RO EDC - Error syndrome register F0C00038 - 1 WO EDC - Clear syndrome F0Dcc0ss B 1M RW 4680 I/O, c=cs, s=strobe F0E000z3 B 1 RW CIO ports and control F0F0z003 B 1 RW SCC control register channel z F0F1z003 B 1 RW SCC data register channel z FFFFFFFF B 1 RO SCC and CIO intack 5.1.2 Resources physically attached to the DMA bus. Base adr & fc Width Size Type Item --------------- ------- ------- ------- -------------------------------- ... 00000000 . B <=1M RW E(E)PROM memory. ... 00400000 . B 1k RW Floppy fifo. ... 0040f000 . B 1 RW Floppy controller (f=2-7). ... 00800s00 . W 2k RW SCSI fifo, data. ... 00800s10 . W 2 RW SCSI fifo, bypass, Not used. ... 00800s20 . W 2 RW SCSI fifo, configuration. ... 00800s30 . W 2 RO SCSI fifo, status. ... 00800s30 . W 2 WO SCSI fifo, command. ... 00C00000 . B 1 WO Control bits. ... 00C00000 . L 4 RO Status register with control bits. ... 00D00003 . B 1 WO Lamp register. ... 00D00003 . B 1 RO Unspecified data. ... 00E00000 . L 32/128k RW RAM memory. 0.. 40000000 0 W 16 RO Move 1 word from SCSI into Pipeline. 0.. 40000000 0 W 16 WO Write 1 word into Pipeline. 1.. 40000000 4+ - 1Gb RW Main bus I/O 0.. 80000000 0 L 16 RO Move 8 words from SCSI into Pipeline. 0.. 80000000 0 L 4 WO Send Pipeline burst to main memory. 1.. 80000000 4+ - 2Gb RW Main bus memory, a30 = maint. mode A more detailed address map including the covered bit patterns are found in the 1143.amap document. Caution has to be taken when choosing access width and address of a resource, due to the differences in bus interfaces between the main processors (MC68040) and the DMA processor (MC68020). 5.2 Cache. 5.2.1 Size & organization. The reasons for implementing a cache are increased speed and decreased bus load. To obtain this goal the hit rate has to be good, which in turn requires the total size of the cache to be fairly big. This cache have a size of 128kb. It is working in the physical address space and is direct mapped. To achieve maximum speed in a MC68040 environment it is mandatory to use the burst read cycle. Actual implementation gives one initial waitstate for every cycle and no waits during the burst. 4 long words will be loaded into the CPU in 6 clocks. (4 normal nowait reads would have taken 8 clocks.) 5.2.2 Features This is a Copy back cache system with a line size of 128 bits. Copy back implies that writes to memory might not be performed until the data is requested for. Every time the MC68040 requests a line not present in the cache, it will be loaded in from main memory using a page mode cycle of 4 times 32 bit. If the used cache entry was dirty it has to be written to memory (pushed). The push operation is performed by hardware. Line requests due to the MOVE16 instruction will not load the cache. Neither will accesses to cache inhibited pages or special accesses like tablewalk, acknowledge or read modify write load the cache. In a copy back cache system snooping will guarantee that correct data is read even if it is only present in one of the caches: The read cycle will be interrupted by the request intervention signal generated by the cache holding the correct data. The correct data will be written to memory and the read cycle can be restarted. Snooping is also used to prevent stale entries: When an invalidate cycle is seen on the bus, the corresponding entry is invalidated. During the invalidation memory operations must wait. (All writes are invalidate cycles.) 5.2.3 Cache states Each cache entry (16 bytes) can be in either of four states: state description ------------------------------------------------------------------ INVALID No valid data in this cache. SHARED Correct data is present in this cache, in memory and might be present in other caches. EXCLUSIVE Correct data is present only in this cache and in memory. DIRTY This is the only correct data in the whole system. 5.2.4 Cache modes The cache system can operate in either of two modes: - The internal write through mode, which is intended to be used for code, shared pages and semaphores. All 4 states are used. - The internal copy back mode, which is intended to be used for "private" data pages. Only INVALID and DIRTY states are used. The internal copy back mode is used when UPA0 = 1. If a page is to be changed from write through mode to copy back mode the internal cache has to be flushed. (Use the CINVP instruction.) 5.2.5 Cache inhibit. Some areas of the physical address space may not be cached for example I/O. In this implementation no I/O, but all main RAM is cached. Accesses to physical addresses which are cache inhibited in the internal cache will not generate line requests and will therefore not get loaded into the external cache. 5.2.6 Error handling If a cache load encounters a bus error, bad data might be loaded into the cache and the bus error handling routine MUST overload this entry with known good data. 5.2.7 Implementation The cache system can be divided into cache data RAM, cache tag RAM and bus tag RAM. The cache data RAM is a 32k by 32 bit synchronous static RAM addressed by CPU addresses A16-2. To make possible to update the cache on CPU writes of units smaller than long word each byte has been given its own byte enable strobe. The cache tag RAM is an 8k by 18 bit fast static RAM addressed by CPU addresses A16 - 4. The data stored in this RAM is a two bit state code, a written bit and CPU addresses A31 - 17, the page tag. The tag information is written at cache load and the state code part of it is updated at every access requiring a bus operation and at snoop operations. During snoop operations the cache tag RAM is addressed by latched bus addresses. The built in comparators compare the actual address A31 - 17 with the stored value. If they match and are not invalid we have got a hit and the cache data is allowed to be used or updated, if not we have got a miss. Missing writes will not update the cache, missing reads and missing line reads generated by the MOVE16 instruction will generate memory read requests and other missing line reads will generate cache load requests. The bus tag RAM is an 8k by 18 bit fast static RAM addressed by bus addresses BA16 - 4. The data stored in this RAM is a two bit state code, a written bit and bus addresses BA31 - 17, the bus tag. The tag information is written at cache load and the state code part is updated at every own bus operation and at every snoop hit. When there is an external cycle on the bus the built in comparators compare the bus addresses BA31 - 17 with the stored value. If they match and it is a read cycle and the state code equals EXCLUSIVE, then we have a snoop read hit which will change the code to SHARED, but if the state code is DIRTY we have a snoop hit which will generate an intervention cycle. If the match is for an invalidation cycle and the state code does not equal INVALID we have an invalidation hit. Invalidation of the bus tag is performed immediately and after synchronization the cache tag and the 68040 internal caches are invalidated. Due to the synchronization invalidation and state code change will take some time and therefore a wait signal is asserted to memory. This will guarantee that no invalidation or state change gets lost. 5.2.8 Cache test and verify. Some extra hardware has been added only to provide test facilities. The tags can be flushed on CPU request by issuing the RESET instruction. Warning: During the RESET instruction tag output is unknown and can generate false interventions. Reads with CPU signal UPA1 high will generate cycles as normal but data will be discarded and instead the cache tag data will be read. Bit Function ------- ----------------------------------------------------- 31-17 Tag 16 Written bit 15-14 State code 13-0 Not implemented, returns unspecified value State code State name ---------- ---------- 00 INVALID 01 SHARED 10 EXCLUSIVE 11 DIRTY 5.3 Main memory subsystem The memory subsystem on the 1143 board consists of a memory interface block located on the main CPU board and a number of memory boards connected to it. The main board can accomodate up to 4 memory boards providing a total memory capacity of up to 1Gb. Each memory board carry up to eight 40 bit wide SIMM modules (in modulus 2 increment). 5.3.1 Memory interface block The memory interface block provides the following functions: - Electrical isolation between main system bus and the memory board stack. - Generation of check bits on memory write operations. - Detection of multiple and correction of single bit errors during memory read operations. - Preserving information describing error location (error syndrome bits and error address) for maintenance purposes. - Generation of memory refresh cycles. - Generation of BERR* on error conditions. - Generation of BERR* on access to page 0 (below address 0x00010000) if enabled in the CIO. This may be used as a null pointer detector. 5.3.2 Memory organization Every memory card contains a 2-pos. jumper field providing 2-bits selection code (inserted jumper sets corresponding bit value to 0). The code makes memory card to recognize both main bus accesses and refresh accesses. For main bus accesses, selection code must match address lines a29 - a28, while for refresh accesses selection code must match refresh code. If both conditions are met in the same time, refresh takes precedense. Note that refresh and standard cycles can be performed simultanuesly on different memory cards. One memory card can carry maximum 256 Mbytes of memory (a27 - a0). This space is subdivided as follows: a) a27 selects between two physically separated memory matrixes, named "M" and "O" in schematics. b) a26 subdivides every memory matrix into two parts, which are electrically separated. Note: on memory boards supporting 16 Mbits Z-type circuits only one part of every matrix, address- ed by a26 = 0 is implemented. c) a25 - a4 represent addresses internal to memory circuits. No- te that a25 - a24 are significant only if 16 Mbits memory circuits are implemented. d) a3 - a2 select memory word within cache line. Different memo- ry circuits are accessed during cache line operations for in- creased speed margins. e) a0 - a1 are used together with operand size information to obtain type of memory operation and control data paths on byte level. Parameters a)-d) select one 40-bits wide word located in 10 memory circuits. Bit error location within a word is given by error syndrome. For details refer to IDT49C465 data sheet and memory card circuit diagram (047-2044-xx). 5.3.2 Access modes Depending on address range, two different access modes to the memory system are provided (as seen from a main CPU): Address range Mode of operation --------------------- -------------------- 00000000h - 3FFFFFFFh standard mode access 40000000h - 7FFFFFFFf test mode access Standard mode accesses result in transfer of data between the main bus and memory boards. Typical operations incorporate long word read and write, partial write if operand is less than a long word, line read and line write. Generation of check bits and testing of syndrome bits is performed by the hardware simultanously with data transfer. Test mode accesses result in transfer of data to or from syndrome bits. Corresponding data bits in memory become rewritten with their previous values. Syndrome information consists of 8 check bits for every long word in memory and for this reason test mode accesses may only be executed using a byte as operand size. Addresses used in this mode must be long word aligned. Test mode accesses can be used for the following purposes: - To test the operation of memory circuits and storing check bits. This test can be performed during start-up or by memory system diagnostic routine. It treats check bits as data. - In diagnostic routine, to introduce errors. To perform this operation, the routine must perform the following steps: - Disable error correction. - Initialize an area by performing any kind of write operation (check bits will be updated accordingly to the data). - Optionally check for possible errors. - Perform a read to test area to obtain value(s) of check bits. - To introduce an error in check bits, modify its value(s) and write back in test mode. - To introduce an error in data bits, write back a modified data, and then previously obtained check bits in test mode. - Enable error correction. Properly operating memory subsystem will indicate and, if possible, correct introduced memory errors. Check if stored error information matches to the expected values. - During system operation, to perform memory scrubbing. Read accesses in test mode will rewrite memory bits with their previous values (read-don't modify-write), or eventually the corrected values. 5.3.3 Bus error conditions Bus error trap is issued on the following conditions: - Attempt to access a nonexisting resource, which result in main bus time-out. Time-out time is 38.4 - 51.2 microseconds. - Uncorrectable memory error, if enabled. This condition can occur on memory reads in standard or test modes, or on memory writes requiring RMW operations (partial write). 6 Hardware implementation details. The way of accessing the various hardware resources on the board, varies somewhat as far as address and size is concerned, depending on which processor that performs the access. The MC68020 (DMA processor, further on called the DMA) will only benefit from the dynamic bus sizing capability when accessing resources attached to the DMA bus. A main processor will further on be called CPU. This chapter will describe details of hardware implementation, and give some hints for programming of I/O drivers. Where bit function is specified, corresponding description refers to bit value = 1. For most resources, at least two addresses are given, one is the address for access from a CPU and the other for access from the DMA. 6.1 Resources attached on the main bus. Resource description syntax: X.X.X Resource name. On bus, Read/Write Address from CPU: 0x00000000-0x07FFFFFF d31-d0, Quad Address from DMA: 0x00000000-0x07FFFFFF d31-d0, Quad | | Active (valid) bus data bits ____| | Port width, byte, word or quad _________| 6.1.1 Main memory. Main, Read/Write CPU: 0x00000000-0x3FFFFFFF d31-d0, Quad DMA: 0x80000000-0xBFFFFFFF d31-d0, Quad This is the main memory in the system consisting of 0 to 1Gb of dynamic ram with error detection and correction. Please note that DMA access to main memory also requires that the function codes is set to "user" (fc = 1 or 2). Setting address bit 30 will enable the memory maintenance mode for scrubbing and testing of the EDC functions. 6.1.2 DMA bus entry. Main, X CPU: 0x80000000-0xBFFFFFFF X, X This is the "hole" where the DMA subsystem appears in the main bus address map. Please note that not all of the DMA bus resources are accessible from the main bus. Only those with address less than 0x40000000 (in the DMA address map). 6.1.3 VME Subsystem. VME extension makes it possible to attach a completely independent VME subsystem to the 1143-XX CPU board. Such subsystem, consisting of VME compatible CPU, memory and interface boards can use VME bus resources as well as portions of 1143-XX memory. On other side, the 1143-XX can access all resources attached to the VME bus without restrictions. The hardware localized on the VME backplane board supports the following functions: - VME signals conditioning - VME bus arbitration - Daisy-chain lines control - VME bus timeout - VME subsystem reset Conditioning logic makes it possible to meet VME bus electrical specification requirements. Arbitration logic resolves VME bus acquisition using "round robin" algorithm among VME-masters while 1143-XX accesses are prioritized. The 1143-XX simulates a level 3 VME-master positioned first in the grant daisy-chain. The "round robin" sequence continues after every 1143-XX access. VME bus timeout logic handles cases when a VME bus master attempts to access a not present slave. Bus timeout will be approximately 19us. Reset of 1143-XX will generate VME signals SYSRESET* and SYSFAIL*. When reset goes inactive SYSRESET* will too, but SYSFAIL* will stay active until commanded inactive by the operating system. Interrupt requests issued by VME interrupters on levels 1 and 4 are recognized by 1143-XX and will be acknowledged and handled there. All other interrupt requests must be handled by local VME resources. When 1143-XX becomes a VME bus master, it can generate the following access types: - byte, word or long word accesses in 64kb range (short address space). - byte, word or long word accesses in 16Mb range (standard address space) - byte, word or long word accesses in 4 Gb range (extended address space) - byte or word interrupt acknowledge accesses AM* bits asserted during 1143-XX accesses describe supervisor data. 6.1.3.1 VME extended space. Main, Read/Write CPU: 0xC0000000-0xCFFFFFFF d31-d0, Quad DMA: 0x40000000-0x4FFFFFFF d31-d0, Quad 6.1.3.2 VME standard space. Main, Read/Write CPU: 0xD0000000-0xD0FFFFFF d31-d0, Quad DMA: 0x50000000-0x50FFFFFF d31-d0, Quad When 1143-XX executing standard VME space access becomes VME bus master, it will set AM bit combination corresponding to standard supervisor data space access. Any address within VME address space can be accessed. Accesses to non responding slaves will result in bus error trap. Any size accesses are legal but long word accesses will be automatically split by the CPU, if not aligned on long word boundary. 6.1.3.3 VME short I/O space. Main, Read/Write CPU: 0xE0000000-0xE000FFFF d31-d0, Quad DMA: 0x60000000-0x6000FFFF d31-d0, Quad As 1143-XX accesses this space, AM5 bit on VME bus will be asserted indicating short address access. Other AM bits correspond to supervisor data access. Any size accesses are legal,but long word accesses will be automatically split by the CPU, if not aligned on long word boundary. 6.1.3.4 VME extended address register. Main, Read/Write CPU: 0xE0200000 d31-d24, Byte DMA: 0x60200000 d31-d24, Byte This register makes it possible for 1143-XX to access entire extended VME address space. After being initiated, it provides VME address bits 31-28 while 1143-XX executes extended VME space access. This register can be read and restored at context switch, as desired. 6.1.3.5 VME interrupt mask register. Main, Read/Write CPU: 0xE0400000 d31-d24, Byte DMA: 0x60400000 d31-d24, Byte This register provides selective enable possibility for VME interrupts. At reset it is cleared, prohibiting interrupts generated on VME subsystem to reach the CPU. In order to enable any particular VME interrupt level, this register must be written with a "1" at bit corresponding to resp. interrupt level. - bit 1 corresponds to interrupt level 1 on VME - bit 4 corresponds to interrupt level 4 on VME Other bits are not supported, as 1143-XX recognize levels 1 and 4 only. This register is readable, but only bits 1 and 4 are valid. 6.1.3.6 VME interrupt readout. Main, Read only CPU: 0xE0500000 d31-d24, Byte DMA: 0x60500000 d31-d24, Byte This port makes it possible to read VME interrupt lines 1 and 4. An asserted interrupt 1 line returns a "0" on bit 1, while asserted interrupt line 4 returns a "0" on bit 4. Other bits return "1". 6.1.3.7 VME interrupt acknowledge. Main, Read only CPU: 0xE0FFFFFv d31-d0, Byte or word DMA: 0x60FFFFFv d31-d0, Byte or word As 1143-XX handles VME level 1 and 4 interrupt requests only, legal "v" values will be 2 and 8 if read word is used, or 3 and 9 if read byte is used. AM* bit combination describes supervisor data access. 6.1.3.8 VME Master accessing system memory Any external VME bus master providing extended addressing capability can access the system memory. The memory can be find at extended access in address range 0x00000000-0x3FFFFFFF. Accesses are prohibited when SYSFAIL* line on VME is asserted by 1143-XX (se p.6.6.2). Until released, attempt to access system memory returns BERR* on VME. For selftest purpose, system memory can be written by 1143-XX accessing extended VME address space. Extended address register must point to a proper address range. A read attempt returns bus error trap. Write result can be obtained reading system memory directly. Note: This function is intended for test only and may hang if accesses come too close. When an external VME bus master trys to read uninitiated system memory, it gets BERR*. Write operation is enhanced using one stage pipeline. Written data, address and control information is stored internally and DTACK* is returned before data is written to memory. This feature greatly improves bus performance. Indivisible operations (TAS or CAS) can be performed using slaves located on VME bus. Accesses to system memory are not guaranteed to be indivisible. 6.1.4 SCSI (Small Computer Systems Interface) channels. The SCSI implementation allows up to three SCSI channels, each consisting of one Adaptec AIC6250 SCSI interface chip, one 1Kb x 16(18) IDT72521 fifo memory and one pal circuit. The SCSI chips are accessed from the main bus and the fifo memories from the DMA bus. Please note that the "A" port of the AIC chip should be configured as an output port, where bit 0 (zero) is used to gate the respective interrupt to the CIO. A logic "1" will pass the interrupt further on to the CIO. 6.1.4.1 SCSI chips address register. Main, Write only CPU: 0xF0000s03 d7-d0, Byte DMA: 0x70000s03 d7-d0, Byte s = SCSI channel number (0-2). This port writes a register pointer into one of the three SCSI channel control chips. Refer to Adaptec AIC6250 data sheet for details. 6.1.4.2 SCSI chips data register. Main, Read/Write CPU: 0xF0000s13 d7-d0, Byte DMA: 0x70000s13 d7-d0, Byte s = SCSI channel number (0-2). This port reads from or writes to, the selected data register in one of the three SCSI channel control chips. Refer to Adaptec AIC6250 data sheet for details. 6.1.5 CPU attention registers. Main, Read/Write CPU: 0xF0C0n000+3 d7-d0, Byte DMA: 0x70C0n000+3 d7-d0, Byte n = CPU number 0-4(5). Write access to those registers makes it possible to assert/deassert IRQ level 5 (attention) on each CPU plane. Assert/deassert function is defined by d7 at write: d7 = 1 assert IRQ d7 = 0 deassert IRQ Read access to those addresses returns the following values: IRQ not asserted: value = 0x00 IRQ asserted: value = 0xFF 6.1.6.1 Ethernet channel attention. Main, Read only CPU: 0xF0C00010 -, Any DMA: 0x70C00010 -, Any Reading this port will activate the channel attention signal on the Ethernet contoller chip (82596CA). 6.1.6.2 Ethernet port access. Main, Write only CPU: 0xF0C00010 d31-d0, Quad DMA: 0x70C00010 d31-d0, Quad Writing this port will deassert the reset signal on the Ethernet controller chip (if active) and write to the port register in the Ethernet controller chip (82596CA). The status of the reset signal may be read in the DMA status register bit 15. Bit Level Mnem Function ------- ------- ------- ------------------------------------- 15 1 erst Ethernet controller chip reset active 6.1.7 Watchdog kick. Main, Read only CPU: 0xF0C00020 -, Any DMA: 0x70C00020 -, Any Watchdog kick. Watchdog timeout is 1.2 seconds while early warning (NMI) will be asserted 1 second after the most recent access to this port. 6.1.8 Timer interrupt reset. Main, Write only CPU: 0xF0C00020 -, Any DMA: 0x70C00020 -, Any Timer interrupt reset. 6.1.9.1 EDC - Configuration register. Main, Write only CPU: 0xF0C00030 d25-d24, Byte DMA: 0x70C00030 d25-d24, Byte This port holds the configuration bits for the main memory EDC functionality. Bit Level Function ------- ------- ----------------------------------------- 25 1 Enable BERR* reply on uncorrectable error 25 0 No BERR* reply 24 1 Return corrected memory data at read 24 0 Return raw (ucorrected) memory data at read These bits are set to 0 at power on. 6.1.9.2 EDC - Error syndrome register. Main, Read only CPU: 0xF0C00030 d31-d0, Quad DMA: 0x70C00030 d31-d0, Quad Bit Level Function ------- ------- ----------------------------------------- 31-24 X Undefined 23 1 Flag E - Correctable memory error 22 1 Flag M - Uncorrectable memory error 21 1 Flag N - Multiple errors encountered since last check 20 0 Always zero 19-16 X Undefined 15-8 value Error syndrome, for bit identification see IDT49C465 data sheet. 7-6 0 Always zero 5-4 value Memory board number (address bits 29-28) 3 value Memory matrix ID (address bits 27) 2-1 value Memory module ID (address bits 26 and 3) 0 value SIMM module side (address bit 2) The flag bits (bits 23-21) in this register are cleared (set to zero) after it has been read. 6.1.10 Main processors reset. Main, Read/Write CPU: 0xF0C00703 d7-d0, Byte DMA: 0x70C00703 d7-d0, Byte Write access to those registers makes it possible to assert/deassert the RST condition on CPU planes 0-4(5) (note, ALL planes). Assert/deassert function is defined by d7 at write: d7 = 1 assert RST d7 = 0 deassert RST Read access to those addresses returns the following values: RST not asserted: value = 0x00 RST asserted: value = 0xFF 6.1.11 DataBoard 4680 I/O Subsystem. Main, Read/Write CPU: 0xF0Dcc0ss d31-d24, Byte DMA: 0x70Dcc0ss d31-d24, Byte cc = Channel select code, see below. ss = Strobe, see below. For DataBoard read accesses, the byte of data will also appear on data bits d15-d8. The number of 4680 I/O boards supported is limited by number of CSB* signals which the system can recognize. This number is limited to 3, which means that the system can handle the following board combinations: - two standard boards - one standard board and one expansion board 6.1.11.1 Board selecting. Board select sequence (select code and CS* strobe generation) is performed automatically at every 4680 I/O access. Standard select codes (cc) in range 0x00 to 0x3F are defined by address bits a17-a12 which makes it possible to protect boards against unauthorized accesses. Special read functions (CSB* and EXP*) will be invoked when a18 is high (when cc = channel select code + 0x40). Select codes in range 0x80 to 0xBF are used to address some special 4680 I/O boards with extended select code facility. 6.1.11.2 Strobe generation Strobes generated in the subsystem are defined by address bits a2-a4. Assuming address values in range 0x00 to 0x1F, the following strobes will be generated: Read strobes: Note! Data will appear on d31-d24 and d15-d8 ss = 0x00 INP* ss = 0x04 STAT* ss = 0x08 OPS* ss = 0x00 CSB* read (when cc = select code + 0x40) ss = 0x10 EXP* ( " " " ) Write strobes: ss = 0x00 OUT* ss = 0x08 C1* ss = 0x0C C2* ss = 0x10 C3* ss = 0x14 C4* Note: only byte operands are legal. 6.1.11.3 Interrupt recognition 4680 I/O interrupts are fed to CIO port A:3 - A:1. Expansion interrupt XINT3* is connected to CIO port A:3, making it simple to identify this type of interrupt request. 6.1.12 CIO Details. The Zilog 8536 CIO circuit, clocked at 4.9152 MHz, is used to control NVRAM and battery clock as well as interrupt decoding and miscellaneous control. Refer to Zilog manual for detailed information. 6.1.12.1 CIO Port C. Main, Read/Write CPU: 0xF0E00003 d7-d0, Byte DMA: 0x70E00003 d7-d0, Byte This port supports battery clock and NVRAM functions. It is totally compatible with DS90-41 approach and should be programmed in the same way. 6.1.12.2 CIO Port B. Main, Read/Write CPU: 0xF0E00013 d7-d0, Byte DMA: 0x70E00013 d7-d0, Byte This port supports a number of hardware controls as well as some input signals. Bit Level Mnem Function ------- ------- ------- ------------------------------------- 7 1, Out page0 Generate bus error on access below address 0x00010000 (first 64Kb) 6 0, Out thinwire Select the thinwire LAN interface 5 0, Out idle_ Turn "IDLE" lamp on 4 0, Out vme_en_ Enable VME subsystem (release SYSFAIL*) 3 0, Out poff_ Power off 2 1, In acok ACOK 1 0, In auto_ Key in "AUTO" position 0 1, In dmint DMA interrupt request 6.1.12.3 CIO Port A. Main, Read/Write CPU: 0xF0E00023 d7-d0, Byte DMA: 0x70E00023 d7-d0, Byte This port is used as interrupt encoder for a number of external interrupt conditions. Bit Level Mnem Function ------- ------- ------- ------------------------------------- 7 0, In s0_int_ SCSI 0 interface interrupt 6 0, In s1_int_ SCSI 1 " 5 0, In s2_int_ SCSI 2 interface interrupt 4 1, In fp_int Floppy interface interrupt 3 - 1 0, In xintN_ 4680 I/O interrupts 0 0, In eint_ Ethernet controller interrupt. 6.1.12.4 CIO Control port. Main, Read/Write CPU: 0xF0E00033 d7-d0, Byte DMA: 0x70E00033 d7-d0, Byte This is the control port in the CIO. 6.1.13 Serial communication channels. Main, Read/Write CPU: 0xF0F0z003 Control d7-d0, Byte DMA: 0x70F0z003 Control d7-d0, Byte CPU: 0xF0F1z003 Data d7-d0, Byte DMA: 0x70F1z003 Data d7-d0, Byte Serial communication is supported by Z8530 SCC devices. Two ComC modules are standard, while additional 12, opto isolated channels can be added using 5262-00 communication boards. The hardware supports asynchronous protocols according to RS232 standard. The SCC's are clocked at 4.9152MHz (PCLK) which suits most baudrates. Serial ports implemented on base CPU board have numbers n = 0 and 1. Port numbers 4-15 are supported by 5262 boards. Even "n" values select port B on resp. SCC device, while odd "n" values select port A. 6.2 Resources attached on the DMA bus. The DMA bus holds a MC68020 processor (further on called the DMA), running at main bus clock speed (25MHz), PROM, RAM, led lamps, floppy interface and the data transfer path of the SCSI channels. The DMA is used to start up the system by loading the appropriate code from mass memory into the main memory and then remove the reset condition of the CPU's. The DMA RAM memory is then loaded with the code that makes the MC68020 to act as a pure DMA processor. The function code, fc, should reflect supervisory access (5 or 6) for all accesses done by the DMA processor exept for pipeline operations where fc should be 1 or 2 (user access). 6.2.1 Boot prom memory. DMA, Read/Write CPU: 0x80000000 d31-d24, Byte DMA: 0x00000000 d31-d24, Byte The boot memory in the DS90-47 may be an EPROM or an EEPROM according to the following table where the code should be set on switch S3-S5. Note! The "wallow" bit must be set in the DMA control register to allow write access to the EEPROM. Code Type Size Model Note ------- ------- ------- --------------- --------------------- 0 EEPROM 32Kb X28C256 Xicor or equiv. 1 EEPROM 64Kb X28C512 Xicor or equiv. 1 EEPROM 128Kb X28C1024 Xicor or equiv. 4 EPROM 32Kb 27256 5 EPROM 64Kb 27512 5 EPROM 128Kb 271024 5 EPROM 256Kb 272048 6 EPROM 512Kb 274096 A guess 7 EPROM 1Mb 278192 A guess 6.2.2 Floppy interface. The floppy interface consists of a National Semiconductor DP8473V floppy controller chip, a 1Kb x 8(9) fifo memory and control logic. Please note that bit 4 in the DMA control register is used to gate the interrupt to the CIO. A logic "0" will pass the interrupt further on to the CIO. 6.2.2.1 Floppy fifo port. DMA, Read/Write CPU: 0x80400000 d31-d24, Byte DMA: 0x00400000 d31-d24, Byte This port accesses the floppy interface fifo memory. The fifo is controlled by 3 signals in the DMA control register as follow: Bit Level Mnem Function ------- ------- ------- ------------------------------------- 4 0 fpie_ Enable floppy interrupt to host. 2 0 ffrst_ Fifo reset 1 0 fdirw_ Direction write (to floppy) 0 1 fen Fifo enable A total of four flags is generated from the fifo and is presented in the DMA status register as follow: Bit Level Mnem Function ------- ------- ------- ------------------------------------- 19 0 fdata_ Transfer request flag. 14 0 fff_ Fifo full. 13 0 fhf_ half full. 12 0 fef_ empty. The full, half full and empty flags are derived directly from the fifo chip whilst the transfer request flag is intended to inform that it is possible to transfer 512 bytes in the direction programmed by the fdirw_ signal as follow: fen fdirw_ fhf_ fdata_ Function ------- ------- ------- ------- ----------------------------- 1 X X 1 - 0 0 0 1 - 0 0 1 0 OK to write 512 bytes to fifo 0 1 0 0 OK to read 512 bytes from fifo 0 1 1 1 - 6.2.2.2 Floppy controller chip. DMA, Read/Write CPU: 0x8040n000 d31-d24, Byte DMA: 0x0040n000 d31-d24, Byte n = Floppy controller chip register number. This port accesses the National Semiconductor DP8473V floppy controller chip. Please refer to data sheet for details. The motor on signal (MTRn) pins controlled via the drive control register have some special functions as follow: MTRn Connected to ------- ----------------------------------------------------- 3 Interface pin 2, RPM/LC signal 2 Floppy controller pin 47, DRVTYP signal 1 Interface pin 4, HDLD* signal 0 Interface pin 16, MTRON* signal This special use of the motor on signals will put restrictions on the use of drive select number 2 and 3 since the corresponding motor on signal must be active to enable the selection of the drive. 6.2.3 SCSI fifo channels. DMA, Read/Write The fifo part of the SCSI interfaces consists of one IDT72521 bidirectional 1Kb x 16(18) fifo memory and one pal circuit for each channel. The A side of the fifo is connected to the high part (d31-d16) of the DMA bus and the B side to the 16 bit wide buffer memory path of the Adaptec AIC6250 SCSI controller chip. 6.2.3.1 SCSI fifo channels. DMA, Read/Write CPU: 0x80800sr0 d31-d16, Word DMA: 0x00800sr0 d31-d16, Word s = SCSI channel (0-2) r = fifo register select This port access the SCSI fifo memory IDT72521. Please refer to data sheet for details. The fifo memory have a 6 bit, general purpose I/O register with external pins of which some are used to control the data transfer and fifo status flags. This register have to be setup according to the following table: Bit Dir. Level Mnem Function ------- ------- ------- ------- ----------------------------- PIO0 Out 0 fen_ Fifo transfer enable PIO1 Out 0 dirw_ Direction write (to SCSI) PIO2 - 0 - Not used PIO3 - 0 - Not used PIO4 - 0 - Not used PIO5 - 0 - Not used Each SCSI channel generates a total of five flags and is presented in the DMA status register as follow: Bit Level Mnem Function ------- ------- ------- ------------------------------------- 18 0 s2data_ Transfer request flag, SCSI 2 17 0 s1data_ SCSI 1 16 0 s0data_ SCSI 0 11 X s2fd SCSI 2 fifo flag D 10 X s2fc SCSI 2 fifo flag C 9 X s2fb SCSI 2 fifo flag B 8 X s2fa SCSI 2 fifo flag A 7-4 X s1f_ SCSI 1 fifo flags 3-0 X s0f_ SCSI 0 fifo flags The four flags A-D, is originating from the fifo and all four of them are fully programmable to suit the software routines that performs the DMA transfers. However, the A and B flags have some hardware attached to them and must therefore be programmed accordingly. The B flag controls the transfer between the fifo and the SCSI controller chip according to the following table: fen_ dirw_ sXfb Action ------- ------- ------- ------------------------------------- 1 X X No action 0 X 1 No action 0 0 0 Transfer from fifo to SCSI (write) 0 1 0 Transfer from SCSI to fifo (read) The A flag is used to generate the fifth, transfer request flag as follow: fen_ dirw_ sXfa sXdata_ ------- ------- ------- ------- 1 X X 1 0 0 1 1 0 0 0 0 0 1 0 0 0 1 1 1 6.2.4 DMA control register. DMA, Write only CPU: 0x80C00000 d31,d26-d24, Byte DMA: 0x00C00000 d31,d26-d24, Byte This register contains 8 individually addressable bits with the following functions: Bit Level Mnem Function ------- ------- ------- --------------------------------------- 7 1 dmaint Interrupt main processor 6 1 dmanmi Interrupt level 7 to DMA processor. 5 1 dmahard Interrupt level 6 to DMA processor. 4 1 fpie Enable floppy interrupt to host. 3 1 wallow Allow write to the EEPROM 2 0 ffrst_ Floppy fifo reset 1 0 fdirw_ Floppy direction write 0 1 ffen Floppy fifo enable Data bit d31 is copied to the bit addressed by d26-d24. All bits are cleared (set to 0) at power on and reset. 6.2.5 DMA status register. DMA, Read only CPU: 0x80C00000 d31-d0, Quad DMA: 0x00C00000 d31-d0, Quad This 32 bit register holds all the available fifo and transfer flags, as well as a copy of the 8 bit control register, as follow: Bit Level Mnem Information ------- ------- ------- ------------------------------------- 31-24 X X Control register bit 7-0 23 1 fint Floppy interrupt active 22 0 s2int_ SCSI 2 interrupt active 21 0 s1int_ SCSI 1 interrupt active 20 0 s0int_ SCSI 0 interrupt active 19 0 fdata_ fifo Transfer request flag, Floppy 18 0 s2data_ SCSI 2 17 0 s1data_ SCSI 1 16 0 s0data_ SCSI 0 15 1 erst Ethernet controller chip reset active 14 0 fff_ Floppy fifo full. 13 0 fhf_ half full. 12 0 fef_ empty. 11 X s2fd SCSI 2 fifo flag D 10 X s2fc SCSI 2 fifo flag C 9 X s2fb SCSI 2 fifo flag B 8 X s2fa SCSI 2 fifo flag A 7-4 X s1f_ SCSI 1 fifo flags 3-0 X s0f_ SCSI 0 fifo flags 6.2.6 Display register. DMA, Write only CPU: 0x80D00003 d7-d0, Byte DMA: 0x00D00003 d7-d0, Byte Every bit in this register controls one LED. The purpose is to monitor system status for maintenance personnel. Bit Level Function ------- ------- --------------------------------------------- 7-0 1 Led 7-0 on Reading this register returns unspecified data. 6.2.7 DMA RAM memory. DMA, Read/Write CPU: 0x80FF8000-0x80FFFFFF d31-d0, Quad DMA: 0x00FF8000-0x00FFFFFF d31-d0, Quad 6.2.8 DMA Pipeline operations. DMA, Read/Write The pipeline is a one way, 16 byte pipeline register that will write it's contents to the main memory in a burst write cycle. This function is implemented to increase the DMA capacity and to reduce main bus load. The DMA is the only processor that is allowed to control the pipeline functions. Please refer to appendix B for further details. 6.2.8.1 Flyby 1 word SCSI->PIPE DMA, Read only DMA: 0x40000s0w, fc = user d31-d16, Word s = SCSI channel (0-2) w = Word select, 0x0 = d31-d16 0x2 = d15-d0 Read one word of data from a SCSI FIFO and store in Pipeline registers. The word select address bit selects where the word will appear when later written to the main memory. 6.2.8.2 Write 1 word to PIPE DMA, Write only DMA: 0x4000000w, fc = user d31-d16, Word w = Word select, 0x0 = d31-d16 0x2 = d15-d0 Write one word of data in Pipeline registers. The word select address bit selects where the word will appear when later written to the main memory. 6.2.8.3 Flyby 8 words SCSI->PIPE DMA, Read only DMA: 0x80000s0w, fc = user d31-d16, Quad s = SCSI channel (0-2) w = Word select, 0x0 = d31-d16, start word 0 0x2 = d15-d0, start word 1, warning! Read 8 words of data from a SCSI FIFO and store in Pipeline registers. The word select address bit selects where the word will appear when later written to the main memory. Please note that setting the word select bit to 1, will result in word swap, which is not normally preferred. 6.2.8.4 Send pipeline to memory. DMA, Write only DMA: 0x8mmmmmm0, fc = user d31-d0, Quad m = Main memory start address, quad word aligned. Send all 16 bytes of the pipeline content as a burst write operation to system memory. 7. Forbidden instruction. The RESET instruction must not be used by the DMA processor. Appendix 1. A.1 Functional description of the main bus system. The main bus system supports data transfers between data sources like CPU planes or DMA and system memory and I/O. It provides the following features: - 32 bits bidirectional data path - 32 bits addressing range (4 Gb) - Error and rerun facility - Single and burst transfers - Multimaster operation (up to 9 bus masters) - Synchronous operation - Read cycle intervention protocol for cache coherency The bus system is designed for high data transfer rates. Top speed of data transfer is 80(100) Mb/sec. A.1.1 Bus signals. The bus system consists of the following signal groups: - BD31-BD0 32 bits data bus - BA31-BA0 32 bits address bus - BMC* Indivisible cycle flag - BW*, MC1, MC0 Bus cycle descriptors - BIZ1*, BIZ0* Transfer size descriptors - BACK* Bus cycle completion indicator - BBER*, BRRN* Bus cycle completion status indicators - BRI*, BIV*, WAIT* Cache coherency protocol control - BRQ0*-BRQ8*, BGR0*-BGR8*, BF/B*, AB* Bus acquisition control All bus signals are synchronous in relation to the clock. A.2 Bus arbitration principle. The bus system utilize a central bus arbiter which can handle up to 9 bus masters and it uses a fair arbiter scheme. The following bus masters are defined: - CPU plane 0-5 - VME subsystem - DMA processor - LAN subsystem For every bus master one request line and one grant line is assigned. Common "Bus Free/Busy" (BF/B*) line indicates bus condition for all masters. The master which needs the bus asserts its bus request line if the AB* (arbiter busy) is inactive. The arbiter resolves requests using a priority algorithm and issues next in turn grant line prior to the next clock cycle. The master which gets its grant line asserted performs the following: - Awaits BF/B* line deasserted - Asserts BF/B* line - Releases request line if no following cycles are required. - Asserts address, size and control lines (data lines if write) and performs bus cycle(s) - If bus cycle is completed and bus grant line is still asserted, the master may retain the bus. Deasserted bus grant line indicates that the bus should be released as soon as possible. The bus master will disconnect and deassert BF/B* line, making it possible for another master to get the bus. - Upon intervention, the active bus master will relinguish the bus for a while. See chapter A.3.6.1 This approach assures equal bus access rights for all bus masters. A.3 Bus signals. A.3.1 Data bus. 32 bits bidirectional data bus is almost MC68040 compatible. A.3.2 Address bus. 32 bit wide address bus carries physical addresses generated by current bus master. Byte and word addressing is MC68040 compatible. A.3.3 Bus cycle descriptors. Those lines define type of bus cycle. The following bus cycles are specified: BW* MC1 MC0 Bus cycle type ------- ------- ------- ------------------------------------- X 1 X No operation H 0 1 Single read cycle L 0 1 Single write cycle H 0 0 Burst read cycle L 0 0 Burst write cycle Those lines are granted to be valid until the first BACK* of the current cycle Once a bus cycle is activated, its type has to be latched until the cycle ends. A.3.4 Transfer size descriptors. BIZ1* and BIZ0* lines describe transfer size. Those lines are compatible to MC68020's SIZ1* and SIZ0* as follow: BIZ1* BIZ0* Transfer size ------- ------- --------------------------------------------- 0 1 Byte transfer 1 0 Word transfer 1 1 3 byte transfer 0 0 Long word transfer Transfer size lines must be latched as well. A.3.5 Cycle completion indicators. Those lines define completion status of the current bus cycle. The cycle can be completed successfully, rerun or generate bus error trap. Successful cycle completion is indicated by assertion of the BACK* line. It should be noted that asserted BACK* line means that during read operation data will be valid on the clock edge following this one, on which BACK* line have been intercepted. On write cycles, data must be stable on the bus until and while the BACK* line is asserted. The duration of BACK* asserted is one clock period for normal cycles and four clock periods for burst cycles. Bus cycles which can not be completed directly can be rerun by assertion of the BRRN* line. This approach is useful when responding device can not transfer data within specified amount of time (another bus master will be allowed to access the bus on this condition). Bus cycles which can not be completed successfully result in assertion of BERR* line causing bus error trap. The BRRN* and BERR* signals are sampled at BACK* time, and for read cycles, also one period after BACK*. A.3.6 Cache coherency A.3.6.1 Read cycle intervention. When a bus master performs a main memory read cycle, a caching (inactive) bus master may hold a dirty entry of the requested data. In this case, the inactive master asserts the BRI* signal to make the active bus master relinguish the bus while the dirty data is beeing written to main memory. The relinguished bus master then resumes the bus and proceeds until completion. This sequence is performed without using the bus request and grant lines. A.3.6.2 Invalidation. Caching masters can be forced to invalidate cache entries due to accesses with BIV* signal active. All write cycles and some read cycles have BIV* asserted. During invalidationm the WAIT* signal is asserted by those masters performing an invalidation. B.1 System overview. ____________________ |5 __________________|_ ___ ____________________ | |4 __________________|_ | | _|__________________ 3| | | |3 __________________|_ | | _|__________________ 2| | | | | |2 __________________|_ | | _|__________________ 1| | | |_| | | |0 | | | | 0| | | | |_| | | Main processors |__| | | Main memory | | |_| |_| | Motorola MC68040 __ | | board | |_| |_| 128Kb cache | | | | 256 Mb each |_| |____________________| | | |_________ _______| |<5 | | _________| |_______ |<4 ____________________ | |____| Main memory | |<3 |1 | | ____ and EDC control | |<2 | Main processor |__| | |____________________| |<0 | Motorola MC68040 __ | ____________________ | | 128Kb cache | | |____| | |<------|____________________| | ____ Serial channels | | | | |____________________| | ____________________ | | ____________________ | | |____| |____| | | | VME and DataBoard ____ ____ Real time clock | |<----|____________________| | | | Time of day clock | | | | | NVRAM memory | | ____________________ | | |____________________| | | |____| | | | LAN interface ____ | ____________________ |<----|____________________| | |____| | | | ____ Misc logic | | ____________________ | | |____________________| |____ | | | | |____>| Bus arbiter | | |__________________ | |____________________| | ________________ | | | | | | | ________________| |______ | | | | | | | | | Crossover | | | | | with pipeline | | | |<-------------|________________ ______| | | | | _______| |__________ | | _|__________________ 2| ____________________ | | _|__________________ 1| | | | | | | 0| | | | DMA processor |____| |____| SCSI channels | | | | ____ ____ Adaptec AIC6250 | |_| | Motorola MC68020 | | | | FIFO 2Kb |_| |____________________| | | |____________________| | | ____________________ | | ____________________ | |____| |____| | | Floppy interface ____ ____ Boot prom memory | |____________________| | | |____________________| | | ____________________ | | _____________________ | |____| |____| | | Lamp register _____________ Ram memory 32Kb | |____________________| |_____________________| B.1.1 Pipeline functionality. As used in this DMA implementation, four (4) IDT 29FCT520 pipeline circuit's is used to achieve a 16 byte buffer, used to perform burst write cycles into the main memory. Each chip is configured as four (4) 8 bit registers and a output multiplexor with tri-state output enable. Data is loaded into the pipeline by issuing a shift command, which at the next clock transition will cause the contents of registers to be shifted forward one stage and the contents of stage 0 will be lost. At any time, the contents of one selected register is presented at the output when the enable signal ia active. Refer to the figure below to recognize the functionality of one chip. Clock -------+---------+---------+---------+ Shift -------+---------+---------+---------+ +------- Enable _|_ _|_ _|_ _|_ _|_ | | | | | | | | | | Input --8--| 3 |--8--| 2 |--8--| 1 |--8--| 0 |--8--|0 | |___| | |___| | |___| | |___| | | | | | | |--8-- Output | | +---------8--|1 | | +-------------------8--|2 | +-----------------------------8--|3 | |___| | Select (0-3) -------+ The four chips are connected together as follow: DMA data bus Pipeline Main data bus _______ _______________________________| | | | |__________ dd31-24 _____________ _______________| | | | |__________ bd31-24 | | | | | | | | | load0 --+---->| | | | |<----+---- read | | | |_|_|_|_| | | | | _______ | _____________|_|_________|_____| | | | |_____|____ dd23-16 _______ _____________________| | | | |__________ bd23-16 | | | | | | | | | | | | | | | +---->| | | | |<----+ | | | | |_|_|_|_| | | | | | _______ | | | | |_______________| | | | |_____|____ | | |_________________| | | | |__________ bd15-8 | | | | | | | | | | load1 --+---->| | | | |<----+ | | | |_|_|_|_| | | | | _______ | | |_______________|_____| | | | |_____|____ |_______________________| | | | |__________ bd7-0 | | | | | | | +---->| | | | |<----+ |_|_|_|_| | Output select and clock to all pipe's At single word accesses, address bit 1 will decide in which word the data will be stored and at burst fill operations the word select will toggle for each word. At burst write to the main memory, the entire 32 bit width will be used and 4 long words will be transferred.