920211/Ga 1143.amap Address map for the 1143 CPU board. =================================== MC1,MC0 ### = change . = Bit not decoded. 1x Idle s = SCSI channel number (0-2). 00 Burst f = Floppy register number (2-7). 01 Standard n = CPU number (0-5 (*4)) a = Sub decoded address (of memory or I/O). v = VME interrupt level (1,4 (*2)) z = Zilog chips select bits. ** Main bus resources: aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa 3322 2222 2222 1111 1111 1100 0000 0000 1098 7654 3210 9876 5432 1098 7654 3210 Start addr. Width Size Type Item ---- ---- ---- ---- ---- ---- ---- ---- ----------- --- ------- ------- ------- -------------------------------- 0... .... .... .... .... .... .... .... 00000000 L 2Gb RW Main memory 10.. .... .... .... .... .... .... .... 80000000 - 1Gb - DMA bus 1100 .... .... .... .... .... .... .... C0000000 L 256M RW VME extended space 1101 .... .... .... .... .... .... .... D0000000 L 16M RW VME standard space (16 times) 1110 .... 0000 .... .... .... .... .... E0000000 L 64k RW VME short I/O space 1110 .... 0010 .... .... .... .... ..00 E0200000 B 1 RW VME extended address register 1110 .... 0100 .... .... .... .... ..00 E0400000 B 1 RW VME interrupt mask register 1110 .... 0101 .... .... .... .... ..00 E0500000 B 1 RO VME interrupt readout 1110 .... 1111 1111 1111 1111 1111 vvv0 E0FFFFFv W 2 RO VME intack 1111 .... 0000 .... .... ..ss ...0 ..11 F0000s03 B 1 RW SCSI chip address register 1111 .... 0000 .... .... ..ss ...1 ..11 F0000s13 B 1 RW SCSI chip data register 1111 .... 1100 .... .... .nnn ..00 ..11 F0C00003+(n^8) B 1 RW CPU attention (n = 0-5) 1111 .... 1100 .... .... .111 ..00 ..11 F0C00703 B 1 RW CPU reset control 1111 .... 1100 .... .... .... ..01 .... F0C00010 - 1 WO LAN controller port 1111 .... 1100 .... .... .... ..01 .... F0C00010 - 1 RO LAN controller channel attention 1111 .... 1100 .... .... .... ..10 .... F0C00020 L 1 RO Watchdog kick 1111 .... 1100 .... .... .... ..10 .... F0C00020 L 1 WO Timer interrupt reset 1111 .... 1100 .... .... .... ..11 0... F0C00030 L 1 RO EDC - Error data register 1111 .... 1100 .... .... .... ..11 0... F0C00030 B 1 WO EDC - Configuration register 1111 .... 1100 .... .... .... ..11 1... F0C00038 L 1 RO EDC - Error syndrome register 1111 .... 1100 .... .... .... ..11 1... F0C00038 - 1 WO EDC - Clear syndrome 1111 .... 1101 cccc cccc .... ...s ss.. F0Dcc0ss B 1M RW 4680 I/O, c=cs, s=strobe 1111 .... 1110 ..0. .... .... ..zz ..11 F0E000z3 B 1 RW CIO ports and control 1111 .... 1111 ..00 zzzz .... .... ..11 F0F0z003 B 1 RW SCC control register channel z 1111 .... 1111 ..01 zzzz .... .... ..11 F0F1z003 B 1 RW SCC data register channel z 1111 1111 1111 1111 1111 1111 1111 1111 FFFFFFFF B 1 RO SCC and CIO intack ** DMA bus resources: aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa fff 3322 2222 2222 1111 1111 1100 0000 0000 ccc 1098 7654 3210 9876 5432 1098 7654 3210 210 Start addr. Width Size Type Item ---- ---- ---- ---- ---- ---- ---- ---- --- ----------- ------- ------- ------- -------------------------------- 00.. .... 00.. .... .... .... .... .... ... 00000000 . B <=1M RW E(E)PROM memory. 00.. .... 01.. .... .00. .... .... .... ... 00400000 . B 1k RW Floppy fifo. 00.. .... 01.. .... .fff .... .... .... ... 00402000 . B 1 RW Floppy controller (f=2-7). 00.. .... 10.. .... .... ..ss ..00 .... ... 00800s00 . W 2k RW SCSI fifo, data. 00.. .... 10.. .... .... ..ss ..01 .... ... 00800s10 . W 2 RW SCSI fifo, bypass, Not used. 00.. .... 10.. .... .... ..ss ..10 .... ... 00800s20 . W 2 RW SCSI fifo, configuration. 00.. .... 10.. .... .... ..ss ..11 .... ... 00800s30 . W 2 RO SCSI fifo, status. 00.. .... 10.. .... .... ..ss ..11 .... ... 00800s30 . W 2 WO SCSI fifo, command. 00.. .... 1100 .... .... .... .... ..00 ... 00C00000 . B 1 WO Control bits. 00.. .... 1100 .... .... .... .... .... ... 00C00000 . L 4 RO Status register with control bits. 00.. .... 1101 .... .... .... .... ..11 ... 00D00003 . B 1 WO Lamp register. 00.. .... 1101 .... .... .... .... ..11 ... 00D00003 . B 1 RO Unspecified data. 00.. .... 111. .... .... .... .... .... ... 00E00000 . L 32/128k RW RAM memory. 01.. .... .... .... .... ..ss ..00 ..N. 0.. 40000000 U W 16 RO Move 1 word from SCSI into Pipeline. 01.. .... .... .... .... .... .... ..N. 0.. 40000000 U W 16 WO Write 1 word into Pipeline. 01aa aaaa aaaa aaaa aaaa aaaa aaaa aaaa 1.. 40000000 S - 1Gb RW Main bus I/O 1... .... .... .... .... ..ss ..00 ..N. 0.. 80000000 U L 16 RO Move 8 words from SCSI into Pipeline. 1aaa aaaa aaaa aaaa aaaa aaaa aaaa 0000 0.. 80000000 U L 4 WO Send Pipeline burst to main memory. 1aaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa 1.. 80000000 S - 2Gb RW Main bus memory, a30 = maint. mode In the start address field, U means user function codes and S means supervisor function codes. Notes: o Accesses not covered by this map will result in unspecified data, no action or reset. o The DMA processor must not perform unaligned accesses to main memory. o The DMA processor should normally operate in system mode (Fc = 1..). For pipeline operation, it should operate in user mode (Fc == 0..). Never use Fc == 7, this is reserved for interrupt acknowledge. CPU --> DMA DMA -------> CPU aaaa aaaa aaaa fff aaaa 3322 3322 3322 ccc 3322 1098 1098 1098 210 1098 ---- ---- ---- --- ---- 0... MAIN MEM 00.. ... DMA I/O 10.. 0... DMA 01.. 0.. PIPE word 11.. MAIN I/O 01.. 1.. 11.. MAIN I/O 1... 0.. rd SCSI to PIPE burst 1... 0.. wr 0... PIPE burst to MAIN MEM 1... 1.. 0... MAIN MEM, a30 = maint. mode