910315/Ga 1136.text ** Changes in 2, 6.4.2, 6.4.5 Short hardware description of 1136 SBC ====================================== P R E L I M I N A R Y 1. Scope. This document will briefly describe the hardware concept of the 1136 cpu board. Basic information about the hardware solutions will be given in order to properly develop all necessary hardware test routines, I/O drivers and interrupt handlers. 2. Objectives. The 1136 is a high performance, low cost, Motorola MC68040 based supermicro computer system, primarily intended to support data communication, industrial control and advanced work-station applications. The basic configuration provides the following resources: - MC68040 CPU microprocessor at 32.00MHz - 4, 16 or 64Mb RAM with parity check - 2 opto isolated serial communication channels (RS232) - 2 opto isolated serial communication channels (RS232 or NRZI) - 1 SCSI interface. - Floppy interface. - Ethernet/Thinnet interface. - Extended expansion capabilities. As optional features the following resources may be added: - 4, 16 or 64Mb RAM with parity check. - 12 opto isolated serial communication channels (RS232). - 1 SCSI interface. 3. Highlights. The expansion capabilities provides full-spec VME extension, making it possible for various VME bus masters to access main system RAM, as well as VME bus resources to be accessed by the system CPU. Beside VME extension, the expansion provides support for proprietary 4680 I/O subsystem. Two SCSI interfaces, each utilized by an intelligent SCSI controller chip and 1Kb of FIFO memory provide high speed data transfer between mass storage devices and main memory. The SCSI interface provides multimaster facility which can be useful for sharing mass storage devices among a number of computers, as well as for direct computer-to-computer communication. Floppy interface supports all existing recording standards, like FM and MFM, various data transfer rates (0.25, 0.5 or 1Mbit/sec), different sector lengths and various motor speeds (300 or 360 rpm). Up to 3 floppy drives can be accessed alternately. 4. Logical address space. Maximum logical address space for any program running on the 1136 is 4 Gb. 4.2 Interrupt system structure. The hardware provides the following interrupt sources: Interrupt levels: (A = autovector response, V = vector supplied) CPU: CIO: --------------------------------------- ------------------------------- 1 -A- VME level 1 2 -V- CIO ----------------------------> 0 - Not used 3 -V- SCC 1 - DataBoard int 1 4 -A- VME level 4 2 - DataBoard int 2 5 -A- Not used 3 - DataBoard int 3 6 -A- Real time, 64Hz 4 - SCSI channel 0 7 -A- Parity error, early watchdog 5 - SCSI channel 1 warning and NMI button. 6 - Floppy 7 - Ethernet 5. Physical address space. The hardware solution provides 256 Mb physical address space. All system resources respond for various addresses in the address map and provide either acknowledge, retry or error response. Address translation on system accesses swaps two 128Mb spaces (memory and I/O), and in reality I/O subsystem occupies higher 128Mb part of the address space. After poweron or reset, the BOOT signal will be active (=1) and the address bit 27 inverted. This address translation takes place immediately after startup, and therefore "real" physical addresses are never visible for the user, not even on bootstrap prom level. A global bus timeout logic will generate bus error after 32-48 microseconds. The following table shows how system resources are mapped within the address space when the BOOT signal is inactive (low). Resource Base address(hex) Size(bytes) Width(bytes) Type ----------------------------------------------------------------------- RAM base 0x00000000 <=128Mb 4 RW PROM 0x08000000 <=1Mb 1 RD Floppy fifo 0x08100000 1k 1 RW Floppy controller chip 0x081n0000 8 (n=2-7) 1 RW SCSI 0 fifo 0x08200000 1k 1 RW SCSI 0 chip, data 0x08220000 1 1 RW SCSI 0 chip, pointer 0x08230000 1 1 WR SCSI 1 fifo 0x08300000 1k 1 RW SCSI 1 chip, data 0x08320000 1 1 RW SCSI 1 chip, pointer 0x08330000 1 1 WR CIO port C 0x08400000 1 1 RW CIO " B 0x08401000 1 1 RW CIO " A 0x08402000 1 1 RW CIO control 0x08403000 1 1 WR SCC control reg ch. n 0x0850n000 1 (n=0-f) 1 RW SCC data reg ch. n 0x0850n800 1 (n=0-f) 1 RW Watch-dog kick 0x08600000 1 1 WR Lamp register 0x08600100 1 1 WR System & floppy ctl. 0x08600200 1 1 WR Ethernet control reg. 0x08600300 1 1 WR Parity syndrome read 0x08600000 4 4 RD Parity syndrome reset 0x08600100 1 1 RD Floppy if status 0x08600200 1 1 RD System & ethernet stat. 0x08600201 1 1 RD Ethernet channel atn. 0x08600300 1 1 RD Backplane resources. Resource Base address(hex) Size(bytes) Width(bytes) Type ----------------------------------------------------------------------- VME extended space 0x0c000000 16M 4 RW VME standard space 0x0d000000 16M 4 RW VME short I/O 0x0e000000 64k 4 RW VME ext. addr. reg. 0x0e200000 1 1 RW VME int. mask reg. 0x0e400000 1 1 RW VME int. readout 0x0e500000 1 1 RO VME intack 0x0efffffv 16 2 RO 4680 I/O 0x0FDcc0ss 1Mb 1 RW 5.1 RAM memory. The 1136 board may hold one or two memory boards each having a capacity of 4Mb(2035-01), 16Mb(2035-04) or 64Mb (2036-XX). This will result in a total memory size range of 4, 8, 16, 20, 32, 64, 68, 80 and 128Mb. The memory board mounted in the first position (P5) will appear from address 0x00000000 and as many times as it fits in a 64Mb range. The second board (in P10) will start from address 0x04000000 (64Mb) and appear as many times as is fits in a 64Mb range. This means that a 4Mb memory board mounted on P5, will appear at 0, 4, 8, 12, ... and 60Mb. 5.2 Cache. There is no additional cache implemented on the 1136 board. The memory array supports burst read cycles which will increase system throughput when this is enabled in the CPU. The snooping functions implemented in the MC68040 are not enabled. 6. Hardware implementation details. This chapter will describe details of hardware implementation, and give some hints for programming of I/O drivers. Please note that a byte assembler have been implemented in hardware to compensate for the missing dynamic bus sizing capabilities in the MC68040. 6.1 Main memory. Rd/Wr B/W/T/L 0x00000000 This is the main memory in the system consisting of 0 to 128Mb of dynamic ram with parity check. 6.2 Boot prom memory. Rd/Wr B/W/L 0x08000000 The boot memory on the 1136 board may be an EPROM or an EEPROM according to the following table where the code should be set on switch S6-S7-S8. The jumper field S9 must also be tuned to match the E(E)PROM package size, 1-2 for 32 pin, 2-3 for 28 pin. Note! The "wallow" bit must be set in the system control register to allow write access to the EEPROM (see p.6.13.) Code Type Size Model Note ------- ------- ------- --------------- --------------------- 0 EEPROM 32Kb X28C256 Xicor or equiv. 1 EEPROM 64Kb X28C512 Xicor or equiv. 1 EEPROM 128Kb X28C1024 Xicor or equiv. 4 EPROM 32Kb 27256 5 EPROM 64Kb 27512 5 EPROM 128Kb 271024 5 EPROM 256Kb 272048 6 EPROM 512Kb 274096 A guess 7 EPROM 1Mb 278192 A guess 6.3 Floppy interface The floppy interface consists of a National Semiconductor DP8473V floppy controller chip, a 1Kb x 8(9) fifo memory and control logic. Four bits are needed to control the floppy interface and they are found in the system & floppy control register (0x08600200). Bit Actlvl Mnem Function ------- ------- ------- --------------------------------------- 0 1 ffien Enable floppy fifo interrupt 1 1 fcien Enable floppy chip interrupt 2 0 fdirw* Direction write to floppy 3 0 ffrst* Reset floppy fifo 4-7 X - Used for other fuctions. Data bit d7 is copied to the bit addressed by d2-d0. All bits are cleared (set to 0) at power on and reset. This register may be read thru the system status register (see 6.14). Reading tho floppy interface status port (0x08600200) gives the following information. Bit Actlvl Mnem Function ------- ------- ------- ----------------------------------- 0 1 ffien Floppy fifo interrupt enable 1 1 fcien Floppy chip interrupt enable 2 0 fdirw* Direction write to floppy 3 0 ffrst* Floppy fifo reset 4 0 fef* Floppy FIFO Empty flag 5 0 fff* Floppy FIFO Full flag 6 0 fhf* Floppy FIFO Half Full flag 7 1 fint Floppy controller chip interrupt 6.3.1 Floppy FIFO. Rd/Wr B/W/L 0x08100000 Access to this port reads or writes data from/to the FIFO buffer memory. Please note that invalid data will be read if the FIFO is empty, and data will be lost if the FIFO is full when writing. Make sure that CPU access to the FIFO does not contradict the operation of the controller chip or the FIFO status bits. A fifo interrupt will be generated according to the following table. ffien fdirw* fhf* Int, Function ------- ------- ------- ------- ----------------------------- 0 X X 1 - 1 0 0 1 - 1 0 1 0 OK to write 512 bytes to fifo 1 1 0 0 OK to read 512 bytes from fifo 1 1 1 1 - 6.3.2 Floppy controller. Rd/Wr Byte 0x081n0000 The controller chip used is the National Semiconductor DP8473 which is accessed through this port. Note that n is the register number where values 2-7 are allowed. Please refer to the National DP8473 manuals for detailed information. The motor on signal (MTRn) pins controlled via the drive control register have some special functions as follow: MTRn Connected to ------- ----------------------------------------------------- 3 Interface pin 2, RPM/LC signal 2 Floppy controller pin 47, DRVTYP signal 1 Interface pin 4, HDLD* signal 0 Interface pin 16, MTRON* signal This special use of the motor on signals will put restrictions on the use of drive select number 2 and 3 since the corresponding motor on signal must be active to enable the selection of the drive. 6.4 SCSI interfaces. Each SCSI interface consists of a Adaptec AIC6250 SCSI controller chip, a 1Kb x 8(9) fifo memory and control logic. The SCSI interface implementation is identical to the one on 1135 board exept for the port addresses, 6.4.1 SCSI 0 FIFO. Rd/Wr Byte 0x08200000 Access to this port reads or writes data from/to SCSI FIFO buffer memory. Please note that invalid data will be read if the FIFO is empty, and data will be lost if the FIFO is full when writing. Make sure that CPU access to the FIFO does not contradict the operation of the controller chip or the FIFO status bits. 6.4.2 SCSI 0 controller. Rd/Wr Byte 0x08220000 Rd/Wr Byte 0x08230000 The controller chip used is the Adaptec AIC6250 which is accessed through these ports. Please refer to the Adaptec AIC6250 manuals for detailed information. Port 0x08220000 accesses the register pointer. Port 0x08230000 accesses the selected data register. The B port in the AIC6250 chip are used to control external functions such as interrupt enable, DMA transfer direction and fifo reset. The B port (reg 0x0e) should be configured as an output port (reg 0x08, bit 4 set). The port will have the following functions and active levels: Bit Actlvl Mnem Function ------- ------- ------- ------------------------------- 3 0 dirw* Direction write (to TARGET) 2 0 fien* FIFO interrupt enable 1 0 cien* AIC interrupt enable 0 0 frst* FIFO reset The A port in the AIC6250 chip are used to monitor fifo and AIC6250 interrupt status. The A port (reg 0x0d) should be configured as an input port (reg 0x07, bit 4 cleared). The port will have the following functions and active levels: Bit Actlvl Mnem Function ------- ------- ------- ------------------------------- 7 0 pint* AIC6250 interrupt pin 6 0 hf* FIFO Half Full flag 5 0 ff* FIFO Full flag 4 0 ef* FIFO Empty flag 6.4.3 SCSI 1 FIFO. Rd/Wr B/W/L 0x08300000 Access to this port reads or writes data from/to SCSI FIFO buffer memory. Please note that invalid data will be read if the FIFO is empty, and data will be lost if the FIFO is full when writing. Make sure that CPU access to the FIFO does not contradict the operation of the controller chip or the FIFO status bits. 6.4.5 SCSI 1 controller. Rd/Wr Byte 0x08320000 Rd/Wr Byte 0x08330000 The controller chip used is the Adaptec AIC6250 which is accessed through these ports. Please refer to the Adaptec AIC6250 manuals for detailed information. Port 0x08320000 accesses the register pointer. Port 0x08330000 accesses the selected data register. The B port in the AIC6250 chip are used to control external functions such as interrupt enable, DMA transfer direction and fifo reset. The B port (reg 0x0e) should be configured as an output port (reg 0x08, bit 4 set). The port will have the following functions and active levels: Bit Actlvl Mnem Function ------- ------- ------- ------------------------------- 3 0 dirw* Direction write (to TARGET) 2 0 fien* FIFO interrupt enable 1 0 cien* AIC interrupt enable 0 0 frst* FIFO reset The A port in the AIC6250 chip are used to monitor fifo and AIC6250 interrupt status. The A port (reg 0x0d) should be configured as an input port (reg 0x07, bit 4 cleared). The port will have the following functions and active levels: Bit Actlvl Mnem Function ------- ------- ------- ------------------------------- 7 0 pint* AIC6250 interrupt pin 6 0 hf* FIFO Half Full flag 5 0 ff* FIFO Full flag 4 0 ef* FIFO Empty flag 6.5 CIO details The type field tells how the bit of the port should be configured. IO=inverted output, O=output, I=input and II=inverted input. 6.5.1 CIO port C. Rd/Wr Byte 0x08400000 This port supports battery clock and NVRAM functions. It is totally compatible with the DS90-30 and should be programmed in the same way. 6.5.2 CIO port B. Rd/Wr Byte 0x08401000 This port supports a number of hardware controls as well as some input signals. Bit Actlvl Type Function ------- ------- ------- --------------------------------------- 7 1 IO Enable NMI on RAM parity error 6 1 IO Define even RAM parity 5 1 IO Turn "IDLE" lamp on 4 1 IO Enable VME subsystem (release SYSFAIL*) 3 1 IO Power off 2 1 I Mains voltage present 1 1 II Key in "AUTO" position 0 1 O Boot level address map 6.5.3 CIO port A. Read Byte 0x08402000 This port is used as interrupt encoder for a number of external interrupt conditions. All interrupts except Ethernet are "active low" and must be programmed accordingly. Bit Actlvl Type Function ------- ------- ------- ----------------------------- 7 1 I Ethernet interface interrupt 6 1 II Floppy interface interrupt 5 1 II SCSI 1 interface interrupt 4 1 II SCSI 0 interface interrupt 3 - 1 1 II 4680 I/O interrupts 0 1 II Spare, always high. 6.6 Serial communication channels. Rd/Wr Byte 0x0850nr00 (n below is channel 0-0xf) Control register, read and write 0x0850n000 Data register, read and write 0x0850n800 Serial communication is supported by Z8530 SCC devices. Four channels are standard, while additional 12 can be added using 5262 communication boards. Port 2 and 3 support both synchronous and asynchronous protocols depending on the selected ComC module while the rest of the ports (0, 1 and 4-15) acts acc. to RS232 standard. All SCC devices are fed with a PCLK of 4.9152MHz. Connectors used are compatible to those used on DS90-30. The previously supplied 1231kHz clock is no longer fed to the SCC chips. Serial ports implemented on base CPU board have numbers n = 0,1,2,3. Higher port numbers are supported by 5262 boards. Even "n" values select port B on resp. SCC device, while odd values select port A. Interrupt requests from all channels are "or-wired" and fed to interrupt level 3. 6.7 Watch-dog kick. Write Byte 0x08600000 Write access to this port results in watch-dog kick. Watch-dog timeout is 1.2 sec, while early time-out warning (NMI) will be asserted 1 sec after most recent watch-dog kick access. 6.8 Display register. Write Byte 0x08600100 Each bit in this register controls one LED. The purpose is to monitor system status for maintenance personnel. Bit Function ------- ----------------- 7-0 LED 7 - 0 on 6.9 System & floppy control register Write Byte 0x08600200 This register contains 8 individually addressable bits with the following functions: Bit Level Mnem Function ------- ------- ------- --------------------------------------- 0 1 ffien Enable floppy fifo interrupt 1 1 fcien Enable floppy chip interrupt 2 0 fdirw* Direction write to floppy 3 0 ffrst* Reset floppy fifo 4 1 led1 Lit led1 on panel 5 1 led2 Lit led2 on panel 6 1 led3 Lit led3 on panel 7 1 wallow Allow write to the EEPROM Data bit d7 is copied to the bit addressed by d2-d0. All bits are cleared (set to 0) at power on and reset. This register may be read thru the system status register (see 6.14). 6.10 Ethernet control register Write Byte 0x08600300 This register contains 4 bits with the following functions: Bit Level Mnem Function ------- ------- ------- ---------------------------------------- 0 X X Spare 1 1 ethin Enable Thinwire net interface 2 1 elpbk* Remove ethernet loopback 3 1 erst Release ethernet controller reset All bits are cleared (set to 0) at power on and reset. This register may be read trough the system status register (see 6.14). 6.11 Parity error syndrome read. Read Long 0x08600000 The logic generates and checks for even parity, this to easily detect nonexistent memory. It will generate an NMI interrupt upon parity error (if enabled (6.5.2)) and latch the physical page number for the access causing the error. It also latches information about which bus master was active. Read access to this port returns information about which (if any) memory byte had wrong parity at memory read. Bit Actlvl Function ------- ------- --------------------------------------------- 31 0 Ethernet controller was bus master 30 0 Backplane was bus master 29-28 0 Don't care 27-12 X Physical page number for (first) error 11-8 0 Don't care 7 0 Multiple parity errors. 6 0 Parity error has occurred. 5-4 0 Undefined 3 0 Parity error on memory data 0-7 2 0 -"- 8-15 1 0 -"- 16-23 0 0 -"- 24-31 6.12 Parity error syndrome reset. Read B/W/L 0x08600100 Access to this port clears the parity error syndrome bits and arms the parity check logic. This port may also be used for test purposes, the returned data will be the contents of the byte assembler. 6.13 Floppy interface status. Read Byte 0x08600200 Reading this port gives the following information: Bit Actlvl Mnem Function ------- ------- ------- ----------------------------------- 0 1 ffien Floppy fifo interrupt enable 1 1 fcien Floppy chip interrupt enable 2 0 fdirw* Direction write to floppy 3 0 ffrst* Floppy fifo reset 4 0 fef* Floppy FIFO Empty flag 5 0 fff* Floppy FIFO Full flag 6 0 fhf* Floppy FIFO Half Full flag 7 1 fint Floppy controller chip interrupt 6.14 System & ethernet status. Read Byte 0x08600201 Reading this port gives the following information: Bit Level Mnem Function ------- ------- ------- --------------------------------------- 0 X X Spare 1 1 ethin Thinwire net interface enabled 2 1 elpbk* Ethernet loopback enabled 3 1 erst Ethernet controller reset active 4 1 led1 Led1 is lit on panel 5 1 led2 Led2 is lit on panel 6 1 led3 Led3 is lit on panel 7 1 wallow Allow write to the EEPROM 6.15 Ethernet channel attention. Rd/Wr B/W/L 0x4030000 Access to this port results in activation of the CA signal to the ethernet controller chip. On the first ethernet channel attention after relase of the ERST signal (see 6.10), the LAN chip will fetch information from high fixed memory addresses (0xfffffn). If the 1136 is equipped with 1Mbit DRAM chips you mask these addresses with 0x3fffff to get the address generated to the main memory array. This gives that the LAN chip fixed addresses will be located in the 0-4Mb range in the main memory array. If 4Mbit or 16Mbit DRAM chips are used then the addressing will be straightforward. Please refer to the Intel 82586 LAN controller manuals for detailed information. 6.16 VME Subsystem. VME extension makes it possible to attach a completely independent VME subsystem to the 1136 CPU board. Such subsystem, consisting of VME compatible CPU, memory and interface boards can use VME bus resources as well as portions of 1136 memory. On other side, the 1136 can access all resources attached to the VME bus without restrictions. The hardware localized on the VME backplane board supports following functions: - VME signals conditioning - VME bus arbitration - daisy-chain lines control - VME bus timeout - VME subsystem reset Conditioning logic makes it possible to meet VME bus electrical specification requirements. Arbitration logic resolves VME bus acquisition using "round robin" algorithm among VME-masters while 1136 accesses are prioritized. The 1136 simulates a level 3 VME-master positioned first in the grant daisy-chain. The "round robin" sequence continues after every 1136 access. VME bus timeout logic handles cases when a VME bus master attempts to access a not present slave. Bus timeout will be appr. 12us. Reset of 1136 will generate VME signals SYSRESET* and SYSFAIL*. When reset goes inactive SYSRESET* will too, but SYSFAIL* will stay active until commanded inactive by the operating system. Interrupt requests issued by VME interrupters on levels 1 and 4 are recognized by 1136 and will be acknowledged and handled there. All other interrupt requests must be handled by local VME resources. When 1136 becomes a VME bus master, it can generate the following types of accesses: - byte, word or long word accesses in 16Mb range (standard address space) - byte, word or long word accesses in 4 Gb range (extended address space) - byte, word or long word accesses in 64kb range (short address space). - byte or word interrupt acknowledge accesses AM* bits asserted during 1136 accesses describe supervisor data. 6.16.1 VME extended space. Rd/Wr B/W/L 0x0c000000 When 1136 executing standard VME space access becomes VME bus master, it will set AM bit combination corresponding to extended supervisor data space access. The VME extended address register (p 6.16.4) will supply address bits 24-31 during this access. Any address within the VME address space can be accessed. Accesses to non responding slaves will result in bus error trap. Any size accesses are legal but long word accesses will be automatically split by the CPU, if not aligned on long word boundary. 6.16,2 VME standard space. Rd/Wr B/W/L 0x0d000000 When 1136 executing standard VME space access becomes VME bus master, it will set AM bit combination corresponding to standard supervisor data space access. Any address within VME address space can be accessed. Accesses to non responding slaves will result in bus error trap. Any size accesses are legal but long word accesses will be automatically split by the CPU, if not aligned on long word boundary. 6.16.3 VME short I/O space. Rd/Wr B/W/L 0x0e000000 As 1136 accesses this space, AM5 bit on VME bus will be asserted indicating short address access. Other AM bits correspond to supervisor data access. Any size accesses are legal,but long word accesses will be automatically split by the CPU, if not aligned on long word boundary. 6.16.4 VME extended address register. Rd/Wr Byte 0x0e200000 This register makes it possible for 1136 to access entire extended VME address space. After being initiated, it provides VME address bits 31-24 while 1136 executes extended VME space access. This register can be read and restored at context switch, as desired. 6.16.5 VME interrupt mask register. Rd/Wr Byte 0x0e400000 This register provides selective enable possibility for VME interrupts. At reset it is cleared, prohibiting interrupts generated on VME subsystem to reach the CPU. In order to enable any particular VME interrupt level, this register must be written with a "1" at bit corresponding to resp. interrupt level. - bit 1 corresponds to interrupt level 1 on VME - bit 4 corresponds to interrupt level 4 on VME Other bits are not supported, as 1136 recognize levels 1 and 4 only. This register is readable, but only bits 1 and 4 are valid. 6.16.6 VME interrupt readout. Read Byte 0x0e500000 This port makes it possible to read VME interrupt lines 1 and 4. An asserted interrupt 1 line returns a "0" on bit 1, while asserted interrupt line 4 returns a "0" on bit 4. Other bits return "1". 6.16.7 VME interrupt acknowledge. Read Byte/Word 0x0efffffv As 1136 handles VME level 1 and 4 interrupt requests only, legal "v" values will be 2 and 8 if read word is used, or 3 and 9 if read byte is used. AM* bit combination describes supervisor data access. 6.16.8 VME Master accessing system memory Any external VME bus master providing extended addressing capability can access the system memory. The memory can be find at extended access in address range 0x00000000-0x07FFFFFF. Accesses are prohibited when SYSFAIL* line on VME is asserted by 1136 (see 6.5.2). Until released, attempt to access system memory returns BERR* on VME. For selftest purpose, system memory can be written by 1136 accessing extended VME address space. Extended address register must point to a proper address range. A read attempt returns bus error trap. Write result can be obtained reading system memory directly. Note: This function is intended for test only and may hang if accesses come too close. When an external VME bus master trys to read uninitiated system memory, it gets BERR*. Write operation is enhanced using one stage pipeline. Written data, address and control information is stored internally and DTACK* is returned before data is written to memory. This feature greatly improves bus performance. Indivisible operations (TAS or CAS) can be performed using slaves located on VME bus. Accesses to system memory are not guaranteed to be indivisible. 6.17 DataBoard 4680 I/O Subsystem. Rd/Wr Byte 0x0FDcc0ss cc = Channel select code, see below. ss = Strobe, see below. For DataBoard read accesses, the byte of data will also appear on data bits d15-d8. The number of 4680 I/O boards supported is limited by number of CSB* signals which the system can recognize. This number is limited to 3, which means that the system can handle following board combinations: - two standard boards - one standard board and one expansion board 6.17.1 Board selecting. Board select sequence (select code and CS* strobe generation) is performed automatically at every 4680 I/O access. Standard select codes (cc) in range 0x00 to 0x3F are defined by address bits a17-a12 which makes it possible to protect boards against unauthorized accesses. Special read functions (CSB* and EXP*) will be invoked when a18 is high (when cc = channel select code + 0x40). Select codes in range 0x80 to 0xBF are used to address some special 4680 I/O boards with extended select code facility. 6.17.2 Strobe generation Strobes generated in the subsystem are defined by address bits a2-a4. Assuming address values in range 0x00 to 0x1F, following strobes will be generated: Read strobes: Note! Data will appear on d31-d24 and d15-d8 ss = 0x00 INP* ss = 0x04 STAT* ss = 0x08 OPS* ss = 0x00 CSB* read (when cc = select code + 0x40) ss = 0x10 EXP* ( " " " ) Write strobes: ss = 0x00 OUT* ss = 0x08 C1* ss = 0x0C C2* ss = 0x10 C3* ss = 0x14 C4* Note: only byte operands are legal. 6.17.3 Interrupt recognition 4680 I/O interrupts are fed to CIO port A:3 - A:1. Expansion interrupt XINT3* is connected to CIO port A:3, making it simple to identify this type of interrupt request. 7. Jumpers and connectors (pardon for the bad scaling). Note! S3 (refresh frequency), S6-S7-S8 and S9 (E(E)PROM size selection) is missing, their positions will marked when the layout is done. Note! Each multipole connector has pin 1 marked. _____ _____ _____ _ _________________| P17 |_| P16 |__| P15 |_| |______________________ | |_____1 |_____1 1_____| | | ## ## | | || || _ |___| P13 # ## P11| | 1|P19 1|P18 1 | P14 S5# P12 | | | | | | P8| | # | | _______________ | | # S4 | | |1______________|P9 | | | | | | | | |_| | | | | _________________ | | |_ P10 Memory 1| | | _______________ |_____________| | | |1______________|P7 _______________ _| P5 Memory |_ | | _| P6 Backplane |_ |1________________| | | __________ |1__________________| | ||| | P3 Power | | |||P4 |_________1| S2## | ||| S1## | ||1 _P2 Floppy_ P20 _P1_ | |__________________|1__________|_|1__|_|1___|_______________________| Connectors: Jumpers: --------------------------------------- ----------------------------- P1 - Control panel. S1 - Enable early watchdog P2 - Floppy interface. warning (NMI). P3 - Power supply. S2 - NMI button. P4 - Power control. S3 - Refresh rate for 25MHz CPU. P5 - Memory board. S4 - Enable ethernet clock. P6 - Backplane. S5 - Disable "mains" monitor. P7 - SCSI bus 1. S6-S7-S8 - E(E)PROM size selection. P8 - TTY expansion (5262 boards). S9 - Select E(E)PROM pin count P9 - SCSI bus 0. 1-2 32 pin P10 - Memory board. 2-3 28 pin P11 - Fan power. P12 - Mains monitor (10-20V ac/dc). P13 - Expansion power control. P14 - Cheapernet. P15 - Ethernet. P16 - Printer (tty00?). P17 - Console (tty01?). P18 - ComC module (tty02?) P19 - ComC module (tty03?).