PAL16L8
PAT8038          **-1110-**          MK,85-05-08
DS60 PARITY GENERATION/DETECTION CONTROL

NC1 NC2 NC3 ES1 ES0 MPI ODD NC4 NC5 GND
TST LDR EDR PIN PBL NC6 ER1 MPO ERR VCC

;EQUATIONS:

IF(VCC)      /LDR =  ES1                    ;LATCH DATA

IF(VCC)      /EDR =  ES1*/ES0               ;WRITE - ENABLE DR TO BUS

IF(VCC)      /PBL = /MPI*/ES1*/TST +        ;PARITY BIT TRANSPARENT
                    /PBL* ES1*/TST +        ;  "     "  LATCHED
                    /MPI*/PBL*/TST          ;NO HAZARD

IF(VCC)      /PIN = /PBL* ES1 +             ;READ TEST - LATCHED PARITY
                    /ES0*/ES1 +             ;WRITE - ALLWAYS LOW
                    /MPI*/ES1* ES0          ;NOT WRITE - PREPARE

IF(/ES0)     /MPO = /ODD                    ;WRITE - PARITY BIT TO MEMORY

IF(VCC)      /ERR = /ES1 +                  ;LOW IF NO TEST
                     ES1*/ODD               ;ERROR IF WRONG PARITY

IF(VCC)      /ER1 = /ES1 +                  ;LOW IF NO TEST
                     ES1*/ODD               ;ERROR IF WRONG PARITY
FUNCTION TABLE:

TST ES1 ES0 MPI ODD LDR EDR PBL PIN MPO ERR ER1

;T EE MO   L E PP M E E
;S SS PD   D D BI P R R
;T 10 ID   R R LN O R 1
------------------------
 H HH HH   L H HH Z H H
 H LH HL   H H HH Z L L
 H HL XL   L L HH L L L
 H HL XH   L L HH H H H
 L HX HX   L X HH X X X
 L LL LX   H H LL X L L
------------------------

DESCRIPTION:

THIS CIRCUIT PROVIDES CONTROL OF PARITY ADAPTER IN ORDER TO
SIMULATE EDAC COMPATIBILITY.

INPUT SIGNALS:

ES0 - EDAC S0 CONTROL
ES1 - EDAC S1 CONTROL
MPI - MEMORY PARITY BIT (INPUT)
ODD - PARITY GENERATOR OUTPUT
TST - TEST INPUT (FOR TEST PATTERN ONLY)

OUTPUT SIGNALS:

LDR - LATCH DATA REGISTER
EDR - ENABLE DATA REGISTER OUTPUTS
PIN - PARITY GENERATOR INPUT
PBL - LATCHED PARITY BIT FROM MEMORY
MPO - MEMORY PARITY BIT (OUTPUT)
ERR - PARITY ERROR