Resume - Curriculum Vitae

EXPERIENCE

January 2000 - present : Sr. Principal Engineer

Working at Force 10 Networks (former Turin Networks) in Petaluma, CA. ' Force 10 Networks doign hardware development. Part of logic design team and later hardware team in general. Involved in systems design, requirement development, implementation, bring-up and qualification.
• Managed and led the hardware development of the S60 product from start to finish.
• Managed and led the HW development of the 10GE and 10x 1GbE Ethernet-to-Sonet line cards for the Traverse produce line. Also developed FPGA on the card with embedded processor.
• Part of team doing the 10/100/1000 linecard for Traverse. Developed FPGA for the card.
• Led development on in-house virtual concatenation mapper for Sonet/SDH for both FPGA and structured ASIC.
• Led development and main designer for large 0.18u standard cell ASIC with integrated 3Gbit/s SERDES technology.
Design in Verilog, tools used from Synopsys, Synplicity, and more. Involved in schematic capture and layout reviews. Several patents applied for (US 6,819,686; 6,868,529; 6,999,468; more pending).

January 1998 - December 1999 : ASIC/FPGA designer

Working at Dynarc Inc. as a development engineer. Dynarc was a start-up company which implemented the promising DTM protocol into hardware and software. Their products included network adaptors for speeds starting at 1 GBit/s. Main focus was FPGA design (>30MHz), board-level verification and specification of future designs (ASICs, FPGA, Boards).

August 1996 - December 1997 : ASIC design

Working at Ericsson Mobile Communications AB in Lund as Digital ASIC designer. Ericsson Mobile Communications has over 850 employees in Lund and about 20 engineers working with Digital ASICs. Working in UNIX environment with Mentor Graphic simulation tools and Synopsys synthesis tools. Fair knowledge of the GSM system. Major responsibilities: Processor integration and system design. VHDL used as design language. Completed a whole design cycle (spec->impl->ver->doc) in a large project. Standard cell, 0.35u technology. US patent 6,445,205 awarded for invention.

March 1996 - August 1996

Master Thesis. Analysis of design methods for Sigma-Delta D/A converters. Design of a Sigma-Delta D/A converter for use in GSM phones. Evaluation of design in Xilinx FPGA devices. US patent 6,175,321 awarded for invention. Work conducted at Ericsson Mobile Communications AB.

November 1995 - March 1996

During this period I followed a project course, VLSI Architectures, which was something more than just another course. First we implemented a small 16-bit RISC processor in VHDL, and then I studied the MPEG-1 Layer-2 audio compression algorithm. The algorithm was also implemented in hardware using VHDL.

June 1993 - June 1994

Military Service
Royal Swedish Air Force
Ängelholm, Sweden

EDUCATION

1991 to 1996

Master in Computer Science and Engineering.
Lund University, Lund Institute of Technology.
Master Thesis: Sigma-Delta D/A converters.
Received top grade in over 70% of graded courses.


1989 to 1991

Gullstrandsskolan, Landskrona
Electrical Engineering, High school
Average grade 4.8 (5.0 Best)

SKILLS

Fast learner of new tools, methodology, etc.
Work very well in groups and alone.
Not afraid of new environments and challenges.


Altera and Xilinx FPGAs
ASIC design (standard cell, structured ASICs, Synopsys tools, vendor interaction)
Networking (1G/10G Ethernet, SONET/SDH, Virtal concatenation, packet processing)
Lab work (FPGA/ASIC/board bringup, Logic analyzers, scopes, etc)
Software for lab and logic simulations

INTERESTS

Photography (link 1, link 2)
Family and friends