Contiguous load of words to multiple strided vectors (scalar index)
Contiguous load of unsigned words to elements of two or four strided vector registers from the memory address generated by a 64-bit scalar base and scalar index which is added to the base address. After each element access the index value is incremented, but the index register is not updated.
Inactive elements will not cause a read from Device memory or signal a fault, and are set to zero in the destination vector.
It has encodings from 2 classes: Two registers and Four registers
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
1 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | Rm | 0 | 1 | 0 | PNg | Rn | T | 0 | Zt | ||||||||||||
msz<1> | msz<0> | N |
if !HaveSME2() then UNDEFINED; integer n = UInt(Rn); integer m = UInt(Rm); integer g = UInt('1':PNg); constant integer nreg = 2; integer tstride = 8; integer t = UInt(T:'0':Zt); constant integer esize = 32;
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
1 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | Rm | 1 | 1 | 0 | PNg | Rn | T | 0 | 0 | Zt | |||||||||||
msz<1> | msz<0> | N |
if !HaveSME2() then UNDEFINED; integer n = UInt(Rn); integer m = UInt(Rm); integer g = UInt('1':PNg); constant integer nreg = 4; integer tstride = 4; integer t = UInt(T:'00':Zt); constant integer esize = 32;
<Zt3> |
Is the name of the third scalable vector register Z8-Z11 or Z24-Z27 to be transferred, encoded as "T:'10':Zt". |
<Zt4> |
Is the name of the fourth scalable vector register Z12-Z15 or Z28-Z31 to be transferred, encoded as "T:'11':Zt". |
<PNg> |
Is the name of the governing scalable predicate register P8-P15, with predicate-as-counter encoding, encoded in the "PNg" field. |
<Xn|SP> |
Is the 64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field. |
<Xm> |
Is the 64-bit name of the general-purpose offset register, encoded in the "Rm" field. |
CheckStreamingSVEEnabled(); constant integer VL = CurrentVL; constant integer PL = VL DIV 8; constant integer elements = VL DIV esize; constant integer mbytes = esize DIV 8; bits(64) offset; bits(64) base; bits(PL) pred = P[g, PL]; bits(PL * nreg) mask = CounterToPredicate(pred<15:0>, PL * nreg); array [0..3] of bits(VL) values; boolean contiguous = TRUE; boolean nontemporal = FALSE; boolean tagchecked = TRUE; AccessDescriptor accdesc = CreateAccDescSVE(MemOp_LOAD, nontemporal, contiguous, tagchecked); if !AnyActiveElement(mask, esize) then if n == 31 && ConstrainUnpredictableBool(Unpredictable_CHECKSPNONEACTIVE) then CheckSPAlignment(); else if n == 31 then CheckSPAlignment(); base = if n == 31 then SP[] else X[n, 64]; offset = X[m, 64]; for r = 0 to nreg-1 for e = 0 to elements-1 if ElemP[mask, r * elements + e, esize] == '1' then bits(64) addr = base + (UInt(offset) + r * elements + e) * mbytes; Elem[values[r], e, esize] = Mem[addr, mbytes, accdesc]; else Elem[values[r], e, esize] = Zeros(esize); for r = 0 to nreg-1 Z[t, VL] = values[r]; t = t + tstride;
Internal version only: isa v33.53, AdvSIMD v29.11, pseudocode v2022-09_rel, sve v2022-09_rel ; Build timestamp: 2022-09-30T16:37
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