UQCVT (four registers)

Multi-vector unsigned saturating extract narrow

Saturate the unsigned integer value in each element of the four source vectors to quarter the orginal source element width, and place the results in the quarter-width destination elements.

This instruction is unpredicated.

SME2
(FEAT_SME2)

313029282726252423222120191817161514131211109876543210
11000001sz0110011111000Zn01Zd
NU

UQCVT <Zd>.<T>, { <Zn1>.<Tb>-<Zn4>.<Tb> }

if !HaveSME2() then UNDEFINED; constant integer esize = 8 << UInt(sz); integer n = UInt(Zn:'00'); integer d = UInt(Zd);

Assembler Symbols

<Zd>

Is the name of the destination scalable vector register, encoded in the "Zd" field.

<T>

Is the size specifier, encoded in sz:

sz <T>
0 B
1 H
<Zn1>

Is the name of the first scalable vector register of a multi-vector sequence, encoded as "Zn" times 4.

<Tb>

Is the size specifier, encoded in sz:

sz <Tb>
0 S
1 D
<Zn4>

Is the name of the fourth scalable vector register of a multi-vector sequence, encoded as "Zn" times 4 plus 3.

Operation

CheckStreamingSVEEnabled(); constant integer VL = CurrentVL; constant integer elements = VL DIV (4 * esize); bits(VL) result; for r = 0 to 3 bits(VL) operand = Z[n+r, VL]; for e = 0 to elements-1 integer element = UInt(Elem[operand, e, 4 * esize]); Elem[result, r*elements + e, esize] = UnsignedSat(element, esize); Z[d, VL] = result;


Internal version only: isa v33.53, AdvSIMD v29.11, pseudocode v2022-09_rel, sve v2022-09_rel ; Build timestamp: 2022-09-30T16:37

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