Arithmetic shift right by immediate (unpredicated)
Shift right by immediate, preserving the sign bit, each element of the source vector, and place the results in the corresponding elements of the destination vector. The immediate shift amount is an unsigned value in the range 1 to number of bits per element. This instruction is unpredicated.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | tszh | 1 | tszl | imm3 | 1 | 0 | 0 | 1 | 0 | 0 | Zn | Zd | ||||||||||||
U |
if !HaveSVE() && !HaveSME() then UNDEFINED; bits(4) tsize = tszh:tszl; integer esize; case tsize of when '0000' UNDEFINED; when '0001' esize = 8; when '001x' esize = 16; when '01xx' esize = 32; when '1xxx' esize = 64; integer n = UInt(Zn); integer d = UInt(Zd); integer shift = (2 * esize) - UInt(tsize:imm3);
<Zd> |
Is the name of the destination scalable vector register, encoded in the "Zd" field. |
<T> |
Is the size specifier,
encoded in
|
<Zn> |
Is the name of the source scalable vector register, encoded in the "Zn" field. |
<const> |
Is the immediate shift amount, in the range 1 to number of bits per element, encoded in "tsz:imm3". |
CheckSVEEnabled(); constant integer VL = CurrentVL; constant integer elements = VL DIV esize; bits(VL) operand1 = Z[n, VL]; bits(VL) result; for e = 0 to elements-1 bits(esize) element1 = Elem[operand1, e, esize]; Elem[result, e, esize] = ASR(element1, shift); Z[d, VL] = result;
If FEAT_SVE2 is implemented or FEAT_SME is implemented, then when PSTATE.DIT is 1:
Internal version only: isa v33.53, AdvSIMD v29.11, pseudocode v2022-09_rel, sve v2022-09_rel ; Build timestamp: 2022-09-30T16:37
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