Move and zero two ZA single-vector groups to vector registers
The instruction operates on two ZA single-vector groups. The ZA single-vector groups are zeroed after moving their contents to the destination vectors. The vector numbers forming the single-vector group within each half of the ZA array are selected by the sum of the vector select register and immediate offset, modulo half the number of ZA array vectors.
The vector group symbol VGx2 indicates that the instruction operates on two ZA single-vector groups.
The preferred disassembly syntax uses a 64-bit element size, but an assembler should accept any element size if it is used consistently for all operands. The vector group symbol is preferred for disassembly, but optional in assembler source code.
This instruction is unpredicated.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 0 | Rv | 0 | 1 | 0 | 1 | 0 | off3 | Zd | 0 |
if !HaveSME2p1() then UNDEFINED; integer v = UInt('010':Rv); integer offset = UInt(off3); integer d = UInt(Zd:'0'); constant integer nreg = 2;
<Zd1> |
Is the name of the first destination scalable vector register of a multi-vector sequence, encoded as "Zd" times 2. |
<Zd2> |
Is the name of the second destination scalable vector register of a multi-vector sequence, encoded as "Zd" times 2 plus 1. |
<Wv> |
Is the 32-bit name of the vector select register W8-W11, encoded in the "Rv" field. |
<offs> |
Is the vector select offset, in the range 0 to 7, encoded in the "off3" field. |
CheckStreamingSVEAndZAEnabled(); constant integer VL = CurrentVL; integer vectors = VL DIV 8; integer vstride = vectors DIV nreg; bits(32) vbase = X[v, 32]; integer vec = (UInt(vbase) + offset) MOD vstride; for r = 0 to nreg-1 bits(VL) result = ZAvector[vec, VL]; ZAvector[vec, VL] = Zeros(VL); Z[d + r, VL] = result; vec = vec + vstride;
When PSTATE.DIT is 1:
Internal version only: isa v33.53, AdvSIMD v29.11, pseudocode v2022-09_rel, sve v2022-09_rel ; Build timestamp: 2022-09-30T16:37
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