SQCVT (two registers)

Multi-vector signed saturating extract narrow

Saturate the signed integer value in each element of the two source vectors to half the orginal source element width, and place the results in the half-width destination elements.

This instruction is unpredicated.

SME2
(FEAT_SME2)

313029282726252423222120191817161514131211109876543210
1100000100100011111000Zn0Zd
U

SQCVT <Zd>.H, { <Zn1>.S-<Zn2>.S }

if !HaveSME2() then UNDEFINED; constant integer esize = 16; integer n = UInt(Zn:'0'); integer d = UInt(Zd);

Assembler Symbols

<Zd>

Is the name of the destination scalable vector register, encoded in the "Zd" field.

<Zn1>

Is the name of the first scalable vector register of a multi-vector sequence, encoded as "Zn" times 2.

<Zn2>

Is the name of the second scalable vector register of a multi-vector sequence, encoded as "Zn" times 2 plus 1.

Operation

CheckStreamingSVEEnabled(); constant integer VL = CurrentVL; constant integer elements = VL DIV (2 * esize); bits(VL) result; for r = 0 to 1 bits(VL) operand = Z[n+r, VL]; for e = 0 to elements-1 integer element = SInt(Elem[operand, e, 2 * esize]); Elem[result, r*elements + e, esize] = SignedSat(element, esize); Z[d, VL] = result;


Internal version only: isa v33.53, AdvSIMD v29.11, pseudocode v2022-09_rel, sve v2022-09_rel ; Build timestamp: 2022-09-30T16:37

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